DFT Digest

Happy Sunday! Test week is over, participants are back to their normal lives, perhaps off to another conference. Last time I blogged, it was Monday, after the first panel and 40th year reception. I’m going to try to blog a few notes throughout this week, including some from conversations with folks from Cadence, Mentor and Synopsys.

It may take me a couple of weeks to crawl through what I saw and heard in my 3-4 days at ITC this year – many of the articles written by the trade press have already (I’ll be linking to them as I see them). Likely by next week, you won’t see any more ITC stories. But you will here – DFT Digest – the gift that keeps on giving? he he… well one thing for sure, your not likely to find any personalized accounts in those stories as you will in mine. That’s what makes blogging fun!

Q: So what do steak, jugglers and analog fault models have in common?

Wow, it’s been so long since I done “in-the-news”, this might get to be a long post… the DFT world moves on whether I have time to document it or not!

The following are a selection of press releases from the first quarter of this year; I’ll follow up with more DFT in-the-news – beacause there is more to the industry than press releases!

Wang, Laung-Terng, Charles E. Stroud, Nur A. Touba
System-on-Chip Test Architectures (Systems on Silicon)
Morgan Kaufmann- Nov, 2007

I’ve previously reviewed VLSI Test Principles and Architectures, edited by L.T. Wang, Chen-Wen Wu, and Xiaoqing Wen, and I’ve got to say, that book along with System-on-Chip Test Architectures, for the price, put an amazing of information at the fingertips of Design, Test and DFT engineers. I’ve said this before in DFT Digest, and I’ll say it again. For the most part, engineering and technical books are prohibitively expensive.