The week’s gotten away from me and without even a mention of the VLSI Test Symposium (VTS 2008). I’m ashamed… can’t keep up.

VTS was held in Rancho Bernardo, CA (just outside of San Diego), from 4/27 to 5/1. The program looked good. In fact, I’ll go out on a limb and say that for VLSI DFT guy like me, there was as much good content at VTS this year as the most recent ITC (and the tequila cruise to baja didn’t hurt, either). Of course, any one of you out there reading this can rightfully call BS on me, since I attended neither event. Too busy DFT’ing lately.

Anyone out there attend? I’d love to hear your impressions..,

In the past there have been requests to address analog/Mixed-signal Design for Test on this blog.  I’ve tried to incite discussion on the subject a couple of times in previous posts (here and here) - limp efforts, at best. To be honest, I wasn’t able to come up with much beyond the mantra of all DFT engineers: maximize controllability and observability.  But that doesn’t mean there wasn’t plenty going on - just that I wasn’t paying attention.  Well, sort of.

At least one commenter to my posts dredged up the name Opmaxx; It’s the name of a company founded in the mid/late 90’s to create products for analog and mixed-signal ‘design centering’ and test automation.  I remember it because it came about just as I was getting more involved in DFT and starting to pay attention to the industry.  One of the products introduced by Opmaxx was called BISTMaxx; it inserted structures that subdivided any circuit into blocks that were then isolated during test mode and turned into oscillators.  The underlying concept is that faulty circuits would produce different oscillation frequencies than good circuits.  The general term for this method is called oscillation BIST.

I know of at least one instance (takes you to an article - scroll down to ‘Test Challenges’) where someone put this into their chips and into production.  Opmaxx was acquired by Fluence, then a subsidiary of Credence, was later absorbed into another Credence acquisition called IMS.  At one point, I believe they were selling BIST products for DACs, ADCs, VCOs and PLLs.  Eventually, at a time I’m unable to pinpoint, Credence dropped these products.  The industry was either not ready or unwilling to accept them, I guess.

However, still in the MS-DFT game was, and is, LogicVision.  I don’t know if they ever had ADC/DAC BIST, although Stephen Sunter (director of mixed-signal and parametric test at LogicVision) has presented papers regarding algorithms for implementing it.  They have had, and still do have A PLL BIST solution, and recently they have developed a SerDes BIST solution, based on undersampling, that claims to achieve sub-picosecond accuracy on any tester.  The SerDes BIST is based upon looping transmit data back through the receive channel, while varying certain parameters - thus being able to actually characterize the ‘eye’ of the signal… (more…)

What is DFT? Many designers just say it’s a pain in the ass. But TMAG has a more accurate description in mind. And they’d like to know if you agree. I blogged a few days ago about the 4/1 general meeting of TMAG (Testability Management Action Group). Well, the ‘Beyond DFT’ committee of said organization discussed/debated some basic definitions (presumably at this last meeting) as a basis of understanding. I would think it’s important that the members of any initiative all be reading from the same page. Here are the definitions they’ve put forward:

Testability is a property of a circuit that enables one to test it easily, or in some cases to test it at all, by being able to control and observe signal nodes that are buried within the circuit.

Design for Testability (DFT) is a methodology incorporated in the design of electronic circuits which takes into consideration the post-design testing phase, and which attempts to reduce the effort and cost of testing.

Structured Design for Test (Structured DFT) is a design technique, usually for ICs, which enables tests to be created automatically or algorithmically. One example of is the design of an IC with a scan structure that enables test for structural faults using a predefined test methodology. While the test may be long, it can be generated without test engineering involvement and test patterns created by computer programs can ensure nearly 100% fault detection of certain fault types.

Built-In Self-Test (BIST) is a method of design – generally for ICs – whereby the mission circuit tests itself. Though this is seldom performed strictly without additional circuitry, if the entire circuitry performing the test is contained within an IC, we call it self-test, in situ test, or built-in self-test.

Built-In Test (BIT) is similar to BIST in that it performs test of the circuit it resides in, but it is generally used at board and system levels and often uses extra hardware, software, and/or firmware to implement the test. When the added circuitry is substantial, it may be called embedded test. If BIT is implemented in software, it is called BIT software.

So what do you think? Send your opinions to LouisUngar@tmag4dft.org. Keep it constructive. Wanna know what I think? Well, it’s my blog, and you don’t have a choice, unless you re-direct your browser now… oh wait. One note before you move on: As this group gets off the ground, they are looking for support to pay the lawyers. Individual memberships are only $24, so make your pledge today. Just send an e-mail to Scott.Davidson@tmag4dft.org to advise him of your intend to support this noble cause. Now read on to see my opinions…

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Registration is open for the Southwest DFT conference, held this time each year in Austin, TX - hosted by SiliconAid Solutions, and sponsored by Cadence, Mentor and Synopsys.  Registration is on a first come, first serve basis, so sign up while there’s room!

The conference is a 2-day event, consisting of a day of tutorials, and a day of presentations given by DFT and EDA engineers. Tutorial day will cover 3 core-test related IEEE standards:

• IEEE 1500 - Teresa McLaurin, ARM
• IEEE 1450.6 - Rohit Kapur, Synopsys
• P1687 - Al Crouch, Asset Intertech

The second day will begin with a keynote speech by Tom Williams of Synopsys, and will be followed by presentations on such great topics, such as variability and defects, testing High-speed interfaces, TAMs for multiple cores, and 1149.6 design considerations. You can check out the full listing of the proposed agenda at the SiliconAid website.

The line up looks fantastic, and every presentation looks interesting to me.  Wish I could be there. Both days are free if you sign-up online, but the second day is $25 at the door if you don’t register ahead of time.

May I be the first to call for the removal of the ‘T’ in DATE (Design Automation & Test in Europe)? If you read the trade press, there was no Test there! DATE 2008 came and went, and for those of us interested in Test - if you weren’t lucky enough to attend - well, it may as well not have even happened. One out of seven technical tracks was dedicated to test issues, but precious little energy was spent by the ‘legitimate’ trade press regarding any test-related activity at DAtE. Oh, I did see one word-for-word regurgitation of Atrenta’s announcement of a DFT-related tool enhancement supporting RTL analysis for transition faults and low at-speed fault-coverage. Good thing we had a ‘journalist’ to vet that story out…

DAC will be the same this year - according to the published conference program, there is exactly one session that is test-related, grouped together with about ten verification events/sessions, under the heading ‘Verification and Test’. DFM garners slightly more mindshare. I guess that’s fine. At least DAC doesn’t have ‘Test’ in the name of their conference.

So what do you think, Test and DFT folks? Are we not stepping up to the plate and contributing? Or is the existence of test-related categories in these conferences just a token nod to us guys on the other side of the wall between design and test?