DFT Digest

… here are a couple of interviews from Test & Measurement World,

ITC Tutorials Span DFT Basics to RF Test, with Rob Aitken of ARM,

and an earlier one,

ITC To Address Expanding Test Role, with Anne Gattiker, Program Chair

Saw this in EETimes online yesterday…
Synopsys claims tripling of TetraMAX ATPG tool performance

DFT Digest is not a news blog, in general, but that’s probably good, because DFT news doesn’t happen quite often enough to blog it. But I’m guessing that this coming month, with ITC week coming, there’ll be some coverage I can pass on.

Shocking…

Math Teacher Arested
NEW YORK — A public school teacher was arrested today at John F. Kennedy International Airport as he attempted to board a flight while in possession of a ruler, a protractor, a set square, a slide rule and a calculator.

At a morning press conference, Attorney General Alberto Gonzales said he believes the man is a member of the notorious Al-gebra movement. He did not identify the man, who has been charged by the FBI with carrying weapons of math instruction.

“Al-gebra is a problem for us,” Gonzales said. “They desire solutions by means and extremes, and sometimes go off on tangents in search of absolute values. They use secret code names like ‘x’ and ‘y’ and refer to themselves as ‘unknowns’, but we have determined they belong to a common denominator of the axis of medieval with coordinates in every country.

As the Greek philanderer Isosceles used to say, “There are 3 sides to every triangle.”

When asked to comment on the arrest, President Bush said, “If God had wanted us to have better weapons of math instruction, He would have given us more fingers and toes.”

White House aides told reporters they could not recall a more intelligent or profound statement by the President.

This has been making the rounds on the internet lately. Don’t know its original source, but it made me laugh… [JMF]

I’ve run across a couple of items in my reading lately about concerns with test-mode power. Not that it’s a new issue, but sometimes when you’re looking for something else, a subject will jump out you a couple of times, causing you to take notice.

Much has been studied and written about test-mode power consumption in the past few years, especially as “at-speed” scan methods have matured and become mainstream. Several different approaches have been considered for dealing with it. DFT tool vendors offer “power-aware” products to mitigate the effects.

The idea is that during ATPG, for example, or logic BIST, most if not all the flops in the device are toggling at once, perhaps for an extended period of time. The massive power draw due to above normal switching activity may cause damage to the device, resulting in reliability failures, and/or lower than normal yield at time zero, especially during at-speed test. Instantaneous switching power can cause voltage drop in the power grid, slowing down the logic and causing false negative results.

I think a good discussion of the different aspects of this issue and methods for mitigation is in order - it also ties into our on-and-off discussion of DFM issues.

More on this later…

When I last left off in this series, we were talking about the broadcasting of scan data from a few external scan chains across many internal parallel scan chains, and some of the ways it is implemented. Not too much detail, but enough to present the concept. So far, all high-level DFT.

Well, once the data has propagated through these much shorter chains, the data must be compressed back into the width of the external scan data paths. Like in the case of decompressing the data, there are a couple of alternatives here, some combinational, some sequential. The combinational implementations are XOR-trees, and the sequential implementations are as you might expect, some sort of MISR. Each has it’s advantages and disadvantages.

(more…)