DFT Digest

Tonight there will be all manner of kids, big and small, traipsing through your neighborhood, masquerading as one thing or another. Be kind, or be tricked… Last week, at ITC, I felt a little like a trick-or-treater, walking around dressed up like a real DFT engineer.

Well, yes, I am a DFT engineer, and I have been hanging around the semiconductor test industry for many years, but ITC always makes me feel this way. I’ve actually only been to two ITC weeks. This was my first in 9-10 years. I went to a VLSI Test Symposium once also. And I always feel like a bystander among some very hard-working engineers who are consistently striving to keep the electronic test industry where it should be with respect to other electronics disciplines.

In general, for me, it was a successful trip. I re-connected with colleagues from “past lives”, and met for the first time some others who opened my eyes to new directions for this blog. Everyone I approached with the idea seemed to be supportive and positive. Now if only I can start registering some of these people. However, I will always grant partial immunity for some of those who are busy being one of those hard-working folks mentioned above. Partial.

I’d like to report on everything I saw and heard that migh be of interest, and I probably will, but it will inevitably span several posts. Where to start? Find out beyond the link…

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“… have been greatly exaggerated” - Mark Twain

In an earlier post, I pointed out an observation seen at DeepChip - that Magma’s DFT strategy was MIA. Well, no sooner did the rumor float than the Twain-like comeback is reported here, by Richard Goering at EE Times. Although, Magma has left the BIST market, it is developing its own ATPG solution, targeting small delay defects, as is the trend in ATPG these days.

The article along with their own press release, also reports that Magma will be present at ITC, with demonstrations of its Blast Create flow’s interoperability with DFT/DFM offerings from several other companies, such as LogicVision, Mentor and Genesys Testware.

I’ll be sure to visit and see what form this interoperability takes…

Today, Accellera has approved the Open Compression Interface standard (OCI version 1.0). See the EE Times article by Richard Goering here.

Back in Test Compression Series - Installment #2, I made brief mention of OCI, which is an effort that was undertaken by Accellera due to a need in the industry for flexibilty in test compression solutions. At this time, test compression implementations come in tightly bound pairs consisting of compression IP and ATPG software; both must come from the same company. This poses problems especially for silicon targeted for more than one foundry, where the different foundries support different yield diagnostics software.

The OCI breaks the need for pairing the IP and software by defining a common interface, which provides just enough information about the compression IP so that any ATPG tool can understand how to generate vectors, but not so much as to give away the secrets of the IP’s implementation.

Next stop, IEEE standards process. Who’s on board?

As I was expecting, as ITC comes upon us, the press releases will start up. Today’s EETimes on-line contains an article entitled “Synopsys Develops New ATPG Technology“. That’ll catch a DFT person’s eye, for sure.

If you read the article, it talks about small delay defects in sub-90nm processes. The new technology will take PrimeTime info and direct the ATPG tool to target paths with the least slack when attempting to catch faults, instead of the easiest ones, which is what current ATPG tools do (probably to make pattern generation faster). Sounds like a good thing to do. I wonder what the ATPG run-time will look like…

This sounds a whole like what Cadence advertises with their Encounter True-time Delay Test, but I haven’t studied that product. Anybody out there have hands-on with it?

Synopsys is not revealing details until ITC, so I guess…

…only time will tell.

A week from today, and ITC will be kicked off in Santa Clara, CA. I’ll be in attendance - specifically, sitting in a tutorial about DF… wait for it … M! Marketing, Manufacturing, Moola, it doesn’t matter, whatever it is, it is driving the forecast for the EDA industry for the next couple of years. See this item in todays on-line version of EE Times. I believe DFM has proven it’s not completely hype; it’s agreed to be absolutely necessary at 65nm and beyond. But I think people also agree it’s the next little tech-bubble, destined for shake-out and consolidation.