Archive for October 2006

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Happy Halloween!

Tonight there will be all manner of kids, big and small, traipsing through your neighborhood, masquerading as one thing or another. Be kind, or be tricked… Last week, at ITC, I felt a little like a trick-or-treater, walking around dressed up like a real DFT engineer.
Well, yes, I am a DFT engineer, and I [...]

Magma DFT – “The rumors of my death…”

“… have been greatly exaggerated” – Mark Twain
In an earlier post, I pointed out an observation seen at DeepChip – that Magma’s DFT strategy was MIA. Well, no sooner did the rumor float than the Twain-like comeback is reported here, by Richard Goering at EE Times. Although, Magma has left the BIST market, [...]

OCI Approved by Accellera

Today, Accellera has approved the Open Compression Interface standard (OCI version 1.0). See the EE Times article by Richard Goering here.
Back in Test Compression Series – Installment #2, I made brief mention of OCI, which is an effort that was undertaken by Accellera due to a need in the industry for flexibilty in test [...]

The PR rolls in…

As I was expecting, as ITC comes upon us, the press releases will start up. Today’s EETimes on-line contains an article entitled “Synopsys Develops New ATPG Technology“. That’ll catch a DFT person’s eye, for sure.
If you read the article, it talks about small delay defects in sub-90nm processes. The new technology will [...]

Countdown to ITC… and M has overshadowed T

A week from today, and ITC will be kicked off in Santa Clara, CA. I’ll be in attendance – specifically, sitting in a tutorial about DF… wait for it … M! Marketing, Manufacturing, Moola, it doesn’t matter, whatever it is, it is driving the forecast for the EDA industry for the next couple of years. [...]