Archive for October 2006
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Magma DFT – Come and gone?
As I was trolling the web for information on some DFM discussion, I tripped upon this post in the latest ESNUG installment over at deep chip, concerning the existence, or lack thereof, of Magma DFT tools. I must say that I also fall into the camp of “those who don’t know a soul who [...]
Clockless Design – Testable?
Just saw this over at EE Times. Being a DFT engineer for many years, steeped in scan methodology, which is inherently ‘clocky’ , I have to ask: how shall we test these designs?
I haven’t done any research on this yet, but I’m curious. I know we all want less power.
Just wondering…
Test Compression Series – Installment #4
Design-for-test methodology and the job of the DFT engineer have grown tremendously in the last few years. The massive amounts of internal circuitry and shear speed at which it operates have outpaced classic ATE’s ability to test it. Therefore, the tester changes residence to within the confines of the device, where it can [...]
Oops!
Just in case you’ve tried to access this site – register and login – in the last week or two, I just found an error that would’ve prevented you from being able to login. I didn’t hear anything, or get any e-mail, so I’ll assume my lack of web-visibility actually worked for me this time!
Anyway, [...]
