As I was trolling the web for information on some DFM discussion, I tripped upon this post in the latest ESNUG installment over at deep chip, concerning the existence, or lack thereof, of Magma DFT tools. I must say that I also fall into the camp of “those who don’t know a soul who use them”.
From the descriptions, it seems as though they tried, but the products never gained momentum. Anybody out there agree/disagree?
Design-for-test methodology and the job of the DFT engineer have grown tremendously in the last few years. The massive amounts of internal circuitry and shear speed at which it operates have outpaced classic ATE’s ability to test it. Therefore, the tester changes residence to within the confines of the device, where it can do a better job. Luckily, the EDA industry’s adoption of smart ideas from the test R&D community (and of course their own research) has stepped up to fill the gap.
Test compression, as we’ve been discussing recently in parts 0, 1, 2, and 3 so far, is an excellent example where internal circuitry eases the requirements of the external tester. ATE tester memory requirements shot through the roof with at-speed scan requirements. A technology requiring the storage of much less test data for the same fault coverage logically follows. Actually, logic BIST falls in this category also, but that’s for another discussion. Here we explore just how much test compression buys you.
Just in case you’ve tried to access this site - register and login - in the last week or two, I just found an error that would’ve prevented you from being able to login. I didn’t hear anything, or get any e-mail, so I’ll assume my lack of web-visibility actually worked for me this time!
Anyway, it’s fixed - comment away!!
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