DFT Digest

You are browsing the archives of 2006 November.

Any good introduction to a topic starts with some discussion of motivation. DFT is no exception. In fact, over the years, most DFT and test engineers have spent more time than they would have liked justifying to designers and design managers the inclusion of test hardware in electronics products.
It’s seemed to me through the [...]

The mission of this website is to educate and discuss electronics design for test. At the end of the day, I want to help anyone trying to tackle the DFT problem, including myself, get through their day. What are we trying to solve? What tools are available to help us solve those [...]

Well, I told myself that as the ITC faded into the past, I was going to delve into the basics – explain to myself and anyone who cares to read how things like scan, ATPG, JTAG, and memory BIST work, and how some of the tools implement them.
But just as I was about to settle [...]

…well at least the marketing folk do, if not the poor integration team or board test team downstream, trying to test your chip, in-situ.
While I was at ITC, I had the pleasure to meet with Ben Bennetts, who, after perusing DFT Digest noticed a distinct lack of material related to JTAG or boundary scan. [...]