DFT Digest

I popped up EETimes today to find this item of interest: “Mentor, Handshake partner on clockless IC testing“. I don’t know how y’all feel, and maybe I’m the last one to the party, but I think this is pretty exciting. The designs I’ve worked on for the last few years, at a couple of different places, have pushed the power envelope to the limit.

I’ve heard about this clockless design approach for several years now, and in fact even alluded to it here on this blog recenlty (see “Clockless Design - Testable?“, from Oct 5, 2005). However, until this latest announcement, have heard nothing about how to test it. According tho the complete press release from Handshake Solutions, they have entered into a reciprocal agreement with Mentor Graphics, and one of the outcomes is that designers using Handshake’s Timeless Design Environment (TiDE) can now create ATPG patterns using Mentor’s FastScan.

A fast browse through Handshake’s website shows that they have partnered also with Cadence and Synopsys for the rest of the design flow. They also market low power HT80c51 microcontroller cores and an ARM996HS core that supposedly uses one-third the power of the normal deal. Very interesting. I’m going to look closer, see what other detail I can dig up, and provide an update here.

Cool stuff…

Unfortunately for me, due to scheduling, I wasn’t able hang out at ITC this year as much as I wanted - and as a result, didn’t get to have many in-depth conversations with folks. I was busy doing a little bit of catching up with a lot of people. The ol’ quantity vs. quality trade off.
However, one short encounter keeps coming back to mind: I talked very briefly with Ken Butler (a colleague from my TI days several years ago). He’s doing some stuff with outlier test these days, and asked me if I had done any more with mixed-signal test improvement, and ways of determining coverage of analog tests, referring to a test quality initiative I was involved in back then.

Well, I haven’t, but a recent press release I read reminded me of our conversation (“Cadence and Advantest Address Zero-Defect Testing Requirements For Automotive Electronics”).

The release is about a partnership between Advantest and Cadence - ATPG technolgy paired up with PAT (Part Average Test) facilities on the ATE. Actually, it was the first time I’d heard the term PAT, and after looking around, saw that it is a form of outlier detection - throwing out die that don’t fit in with the crowd. One way to get to “zero-defect” screening. Maybe we’ll explore these techniques on this blog someday.

So I can see how one could apply some of the newer digital ATPG technologies aimed at small delay defects could help out with zero-defects - better defect coverage is a good thing. But what about the analog circuits?

Back in my TI days, there seemed to be a flurry of activity around mixed-signal DFT, with some new BIST approaches, inductive fault analysis research - IEEE 1149.4 analog boundary scan was being developed at the time. Our own test quality initiative promoted a very manual, but fruitful analog test coverage evaluation that took up to a few days of going through schematics, and deciding whether or not “that transitor over there” was covered by any of the existing tests on the ATE, and if not, what test could we add?

That got us down to about 50 DPM or so, but not zero.

Since then, I’ve gotten away frrom the mixed-signal area, so I haven’t been paying attention. But has anyone done anything to automate that process? Is it possible?

Someone? Anyone?

I started this thread a ccouple of weeks ago, a post - something about writing a DFT plan. My contention was that a testability plan is an outgrowth of the test plan, adding efficiency and coverage.

One comment (thanks, Craig!) on that post got us off to a good start by defining some of the goals and ownership of the DFT plan.

But now I’m going to venture off into the vast terrain of actually deciding what to do for a given design. What kind of design do you have? A small analog design? A big digital design? Many of today’s designs have some of each, right? I think the key is to break down the design into its main components, and then make sure to cover the boundaries.

What I mean by that is that digital circuits have their own applicable techniques, as do analog - but if the boundaries betweeen them are not considered, a loss in fault coverage is bound to occur. We’ll discuss all that later. The point is that subdividing your plan into digital and analog is a good way to start.

Considering the fact that I’m a ‘mostly digital’ guy, that’s where I’m going to start. No worries, I’ll get to the analog - quicker if there are requests - but DFT-wise, digital’s the low hanging fruit and the biggest bang for the buck. How’s that for multiple metaphors?

Let’s explore…

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