DFT Digest

You are browsing the archives of 2006 December.

I popped up EETimes today to find this item of interest: “Mentor, Handshake partner on clockless IC testing“. I don’t know how y’all feel, and maybe I’m the last one to the party, but I think this is pretty exciting. The designs I’ve worked on for the last few years, at a couple [...]

Unfortunately for me, due to scheduling, I wasn’t able hang out at ITC this year as much as I wanted – and as a result, didn’t get to have many in-depth conversations with folks. I was busy doing a little bit of catching up with a lot of people. The ol’ quantity vs. [...]

I started this thread a ccouple of weeks ago, a post – something about writing a DFT plan. My contention was that a testability plan is an outgrowth of the test plan, adding efficiency and coverage.
One comment (thanks, Craig!) on that post got us off to a good start by defining some of the [...]