DFT Digest

Today I received an e-mail from Dr. Ben Bennetts, DFT Consultant (Semi-retired) with a great introduction to some ‘in-the-works‘ extensions to the IEEE 1149.1 test access standard, called IJTAG (Internal JTAG) and SJTAG (System JTAG).

The Internal JTAG effort seeks to standardize the access to ‘internal instruments’ of all sorts that may reside on a single chip. IJTAG has been given permission to work on the standard by the IEEE as P1687.

The SJTAG effort deals with extending test access across several boards, perhaps joined through a backplane, and may include much more functionality than just board-level test, such as system-level configuration.

Much more detail is available in a PDF write-up titled IEEE Testability Standards: Recent Developments, graciously provided by Dr. Bennetts. Please take a look!

If you have questions, you may contact Dr. Bennetts directly, or just comment below, and we will pass it along…

I’m having the hardest time ever keeping up on the blog this month. Call it an extended holiday hangover, crunch time at work, short spates of illness, whatever. I hope February sparks up here for me.

Last month I started writing about testability or DFT planning. Of course, I took the easiest route first. Full scan and memory BIST! Logic BIST! Easy for all digital chips. Didn’t mention JTAG, but I should have, since that’s another area where automated test insertion has worked for many years.

So, yes, we went over the low hanging fruit of the bulk digital logic. Those measures cover the mass of (usually) standard cell, scan-inserted logic. But in every sea of digital circuitry, there are spots where scan insertion is either not possible or imposes an unreasonable timing or area penalty. What methods are available to test this logic?

More after the click…

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Very interesting article over at embedded.com, by Tom Jackson of Cadence Design Systems. He makes some excellent points about the necessity of being aware of power consumption throughout the design flow, including the insertion of test structures. But “Design-With-Test”? What he’s describing is what I thought was termed “Power Aware Design and Power Aware DFT”.

So is Mr. Jackson creating a new design discipline? No, maybe just a new term. Maybe it’ll catch on. Regardless, it doesn’t take away from the points he’s trying to make in the article. Some of them I’ve touch on in earlier posts, such as being aware of the effects of all of the flops on your device being toggled at once during ATPG - it may be more activity than ever seen in functional mode. Test compression may exacerbate the problem, and since test compression is designed in ahead of time, ahead of time is when you need to think about it.

But “Design-With-Test”?

I mentioned in another post just after ITC 2006, that I’d met Ben Bennetts for the first time. We had breakfast, and talked a bit about this blog I was trying to start up. It was an introductory conversation, but secretly, I was hoping to eventually convince him to work up some material on JTAG for the blog. In the end, I’d like to get plenty of contributed material to appear in this blog. Information from the masters of DFT to the masses. That’s what I’m aiming for!

As for Dr. Bennetts, this being his last year before retiring, he’s pretty busy. But he thought the blog was a good idea, and wanted me to make sure to do plenty on board-level test while I was at it. So far, I’ve failed at that. But eventually, I’d like to do some more reading, and be able to put together something coherent.

He also talked some about how over he years he’s pushed very hard to get board-level tracks included in the ITC program. It seemed that device-level issues dominated the space. He pointed out to me that there is plenty going on with board-level test, and standards are currently being worked on to expand the technology of IEEE 1149.1 to new levels, including both the system level (SJTAG), and at the other end, inside the device (IJTAG).

My new friends over at design-for-test.com have also been recipients of Dr. Bennett’s promotional efforts. They have a whole table of the different JTAG standards activities. Hop on over and see it.

Meanwhile, I have some reading to do…

Just tripped on this item while researching for a future post… and apparently it’s fresh:

T.W. Williams, a Synopsys Fellow and true pioneer of modern test methods has been given the European Design Automation Association (EDAA) Lifetime Achievement Award for 2007. The honor is “given to individuals who made outstanding contributions to the state of the art in electronic design, automation and testing of electronic systems in their life.” The link to the press release is here.

In case you’re not familiar with the name, Dr. Williams, along with Edward Eichelberger, published the original paper describing a scan test method using Level-sensitive Scan Design (LSSD) structures, in 1977. He’s published many papers since then building upon that methodology, and has contributed greatly toward establishing scan/ATPG as a de facto standard test methodology. I’d say he’s made my job, and that of many of you out there, much easier.

My hat’s off to you, Dr. Williams - congrats!