DFT Digest

Design for Test is a funny job - it’s like straddling the wall that, in previous generations, designers would throw their designs over to the test guys to write tests…

Traditionally, designers belong to a design group, of course, and test engineers belong to the operations arm of an organization. Both of these roles have a clear objecive, which is backed by the management of the organization they work for. As a DFT guy, I’ve worked for both design and ops at different times.

Who do you work for?

As time goes on, it seems DFT has become more ‘design of test’ than ‘test of design’, if you will. Even as scan test was becoming more popular - you know, last century - it was still part of the implementation rather than of the design; still at the backend of the design, but before test. But today’s technologies are now being planned well ahead of time, from neccessity. So, most of the time the DFT engineer is on the design staff (if not one of the designers).

One thing that can be tough as a design-for-test engineer in a design group is having to stand your ground in the interest of providing efficient test structures on-chip (or on-board), when met with the opposing forces of reducing area, power - and the schedule. It’s sometimes easy for chip leads and design managers to wave off the test design, because they haven’t lived through the extreme hours spent on the ATE debugging tests for untestable devices.

What’s been your experience?

OK, settle down, I know there’s gonna be problems. And to be sure, there are many out there that have already begun to encounter them. Oh, yeah, and then there’s 45nm - I just read today that both Intel and IBM have demonstrated 45nm designs. The article linked is pretty fascinating - but a little dis-heartening to those of us who don’t take advantage of Intel’s or IBM’s processes: the magic in the new technology is in the recipe - single atomic layers of Hafnium-based oxide and metal FET gates, resulting in low-leakage/power designs. Neat. But most of us deal with lagging technology from the commercial fabs.

The question is then, what are the biggest hurdles for testability in these ‘commercially available’ smaller geometries? One DFT Digest reader, Kiran asked me to shed some light on this question. My biggest problem with doing that is simple: I haven’t gotten there yet! Professionally, I haven’t gotten any 65nm chips back yet to see where the DFT broke.

After the click, I’ll tell you what I’m worried about, though (not necessarily in the order of importance, but close): (more…)

And while you’re there, make sure to attend the 2007 SouthWest DFT Conference, hosted by SiliconAid, a DFT consulting services group, based in Austin, TX. This is the 4th year of the annual event, and it features a day-long tutorial, followed by a free technical day, featuring a keynote address, and three technical sessions.

I regret missing this session when I was based in Austin a couple of years ago. It brings together 100-150 DFT and Test professionals from all over the area for some honest to goodness Test and Design for Test talk, not to mention some networking and socializing. Click here for the highlights from last year’s conference.

The event will be held May 30th/31st, at the Omni SouthPark Hotel in Austin.

Check it out…

The DATE (Design Automation and Test in Europe) conference starts today in Nice, France (beautiful place - I have had the fortune of delivering a paper there, for a different conference, several years ago).

If you read this blog, and you are there, check in and give us some updates on what’s interesting!

The keynotes will be given tomorrow, by Dr Tohru Furuyama, of Toshiba Japan, addressing challenges in consumer and mobile SoCs, and Alan Naumann of CoWare, talking about evolution from RTL to system-level design.

So after getting through crunch time at work, I took my family on a short vacation up to the Pacific Northwest. What a beautiful place. Yeah, it rains a lot. But it makes for lots of pretty green stuff… But now it’s crunch time to pay for that week off.

So, while I catch up, you may want to head over to EDA Cafe, where Peggy Aycinena has written an interesting article and interview with Tom Williams (about whom I blogged [1], [2] before). He’s had a distinguished career in DFT.

I found it intriguing that in the same article, Test was described as both “Golden Child of EDA” and “provincial in its separation from the larger world of Design”, and “DFT is walking hand in hand with DFM/DFY and together moving the industry forward.”

I think the EDA world is coming to a slow realization that this thing test, which has been conveniently ignored, then tolerated, is now necessarily integral to the design process. I think it scares them a little…