DFT Digest

Just in case you’re lurking about, and notice some small changes taking place in the look of this website, I should let you kow that I’m testing out a new WordPress theme, which is widget compatible (see the WordPress Codex if this doesn’t make any sense to you). So you might see things appearing and disappearing from the sidebar as I test things out.

I know, I should be spending my time writing about design for test - but I can’t resist the urge to tinker now and then…

From time to time, I go over to EDABoard, a fairly all-encompassing electronic design bulletin board site operated from Europe, and check out the ASIC design forum. It seems that design-for-test is a fairly popular topic over there. There’s plenty of people not even sure where to start with DFT. I try to lend a hand when I can.

The most popular question is “What is DFT?” or “Where do I start?” - “Why add test logic?”. The typical responses from the crowd are of the short form: “DFT = Design-for-Test”, or “check out this book…”, which, to me, are valid responses. A forum is a hard place to explain a whole facet of ASIC design. Believe me, I’d like to write a lot more in this blog, but it’s time consuming, and well… never mind.

But what I find more interesting are the more focused inquiries, where the true misunderstandings are in design-for-test methodology. Looking back over a few pages of topics relating to DFT, I can come up with a few common threads:

• DFT Compiler related questions - Anywhere from trying to figure out why scan chains were not inserted to outright asking for DC scripts, accomplishing the work of scan replacement and insertion is a pretty hot topic.
• Multi-clock domain scan implementations - Many are curious what to do with these, how and when to use lockup-latches, and whether to use one or multiple clocks for the scan chains. Makes for interesting conversation.
• BIST related questions: How to design it, build a bypass, figure out the low fault coverage around BIST implementations. However, people seem to go about it a bit backwards - most don’t seem to know there are tools dedicated to generating BIST for embedded memory.
• Handling of exceptional cases around the scan design, such as bi-directional pins as scan pins, tristate buses
• ATPG verification and simulation mismatches - big topic. What happens when the simulations, or the ATE vectors fail? What’s the likely cause? What format to write? Then what?

Really, a good variety of questions. I’m actually surprised at the frequency of DFT questions popping up on the board - heck, in the larger EDA media, it gets very little mention.

One thing for sure, it’s a great place to pick up a few good interview questions…

I received an e-mail today reminding me of the upcoming SW DFT Conference, sponsored by SiliconAid Solutions, to be held May 31st in Austin, TX. Pre-registration is free until May 25th. No word on what it would cost to register late - I think they make you buy lunch.

All kidding aside, I took a look at their program, and it’s got some good stuff: Keynote by Professor Hank Walker of Texas A&M, who counts defect-based test, delay test and realistic fault modeling among his research interests. Steve Sunter of LogicVision will be talking about BIST-based delay and jitter testing in nanometer technologies - I have checked out their SerDes test product, and I like it. Grzegorz Mrugalski of Mentor will be talking about low power embedded deterministic BIST - a subject of papers by Mentor at both VTS 2007 and DAC 44 next month. Smells like a product rollout to me…

Visit the website to view the entire schedule - including the “Happy Hour During the Panel”. I find alcohol livens up even engineering discussion. Wish I could be there!

Just a shout out to link buddy A.T.E. Solutions - the May 1 newsletter is now available to view (I assume it has been for over a week…) It’s the Design-for-Testability issue, and it has a couple of interesting board-centric DFT articles.  Go check it out.

And it’s May 7th - so I’m late. But not really, because all the action started today, beginning with a plenary session which includes a keynote address by Antun Domic of Synopsys, entitl;ed “New Role of Test in 45 Nanometer”, as well as one called “Roadmap of Design” by Gary Smith.

VLSI Test Symposium focuses on new test technology, and as such, consists of many papers that highlight exciting emerging techniques that you and I, as users of commercial tools, won’t be able to take advantage of right away. However, it is interesting content, and it’s comforting to know that our EDA companies are trying to look ahead to solve our test problems. We need that.

But that said, I should mention that there are some papers that detail methodologies that we can use right away, or will inspire us to do something different in our work, especially with regard to test techniques, outlier detection, and diagnosis.

VTS makes it’s older proceedings online (actually ony the abstracts - you have to pat for the full papers) at the VTS website, and the newer proceedings should be available for order soon (the link wasn’t worrking when I tried it).

I’ll be looking forward to seeing some of these papers. If you’re reading this, and you went to VTS, drop me a line and tell me what you thought was interesting!