DFT Digest

About once a month, Mentor publishes a little piece on their website called Test Talk, written by Al Crouch. This month’s edition, entitled ‘Outsourcing, the Scrabble Method’, is a Dilbertian look at outsourcing, and of course, has its DFT-related tie-in: weighted fault coverage and n-detect. Hmmm… what could weighted fault coverage and outsourcing have in common?

Al Crouch is Chief Scientist and Director of DFT R&D at Inovys - and author of Design-for-Test for Digital IC’s and Embedded Core Systems, a great primer for DFT engineers. He’s also vice-chair of the P1687 (IJTAG) working group. Haven’t met him in person yet, but I know him by sight, and I’ve never seen him without a Hawiian shirt on - you know, perpetual casual Friday - I like his style…

Mr. Crouch also co-wrote chapter 6 of Advances in Electronic Testing: Challenges and Methodologies, which is a fairly new book, that I definitely have to get into my DFT Bookshelf.

I’ve been trying to put together some info about JTAG and boundary scan, but being a chip engineer, I’m having a hard time expanding my mind to the edges of the device lately. However, this item came across my e-mail this week - a free, expanded version (110 pages) of Asset Intertech’s Boundary Scan Tutorial.

You must register to get it sent to you, but it’s FREE ( from experience, I know that word FREE is a huge magnet for engineers, most especially when it precedes FOOD )

As I was at their website signing up for the book, I found, on the same page, links to some great material on boundary scan DFT from both chip and board-level perspectives, developed by Ben Bennetts. Dr. Bennetts retired this year, but his legacy lives on in this great material! Go check it out! Lot’s of information on the many facets of boundary scan ind it’s applications. I wish all EDA vendors had this type of educational content available to the public. Our DFT engineers, more often than not, are not getting this in school.

Alright Asset, I’m waiting by my mail box…

I was just sitting here waiting for a scope tool to draw a simple waveform on this gawdawful 93k ATE, and decided to surf the web a little - and ran across the following entry in Mike Santarini’s blog over at EDN. It seems CMP laid off Richard Goering from EETimes… does the EDA industry get no respect anymore? First Gary Smith’s group gets cut from Dataquest, now this.

I’ve read Richard Goering’s column in EETimes for as long as I can remember. No, he wasn’t into test or DFT particularly, but he covered tools, and you know we all work with tools. Are we supposed to get our EDA news from DeepChip now?

I don’t think so…

I mentioned in my previous post the fact that the design-for-test content was pretty much ITC warmed over. I’m not surprised, mind you. DAC really is more for the overall design & EDA community, whereas the focus of ITC is test. But I saw this article over at the Test & Measurement website that sort of underscores my point.

Four general areas of DFT (or DFM) technology were highlighted in the article. The first area, in my mind, really is a DFM offering. Volume diagnostics or defect diagnostics are terms for tools that most of the big vendors are developing to apply test data back to the layout.

The second, third and fourth areas mentioned are DFT technologies that have been developing over the last 1-2 years, namely, power aware DFT, ATPG for small delay defects, and test compression, all of which I’ve blogged about here at DFT Digest at some point.

Perhaps now would be a good time to cycle though them with some small posts summarizing the offerings from various DFT vendors…

I’ll do that in the coming days…

So, as I was saying, I wandered around DAC for a few hours on Wednesday, and it was fairly quiet, test-wise. Anything I saw there, I saw at ITC in October:

I listened to Tom Williams of Synopsys give a very quick talk on DFT at the submicron level, which, if you blinked, or got distracted in any way, you might have missed a whole sub-topic . If you want to see some of the slides from his talk, you might be able to catch the pictures as part of Peggy A’s article. He showed the Stonehenge pictures to keep us awake. As for DFT, he talked about the limits of test-compression (a subject I still haven’t reconciled in my mind) , picking the worst case paths for transition faults, and the assertion that choosing the most power aware X-fill for ATPG is much easier given the compression architecture of DFT MAX.

Although I wasn’t able to attend, Mentor gurus presented two different test-related papers, one on a new low-power test data compressor, and one detailing an algorithm for generating patterns while considering timing constraints and exceptions.

LogicVision had a fairly low key booth highlighting their BIST solutions.

I stopped by SynTest’s booth and talked to Marketing VP Ravi Apte for a few minutes. SynTest has always been an enigma to me, partly because I live in Southern California, and they don’t have a big presence down here, partly because it’s kind of hard to get much more than datasheet level information about their tools unless you’re a customer, and partly because I’ve never met anyone that uses their tools… not the fault of SynTest - I hear they’re big in the bay area, and in the Pacific rim. If any of you out there are SynTest customers, I’d love to hear what you think of their tools. According to Mr. Apte, they’ve got a full DFT offering, except they’re much more reasonably priced. Oh yeah, and they’ve got the only viable fault simulator out there, that I know of.