DFT Digest

If I may state the obvious, I am one guy, who has led one career, and therefore has a limited base of experience from which to draw. So when it comes to writing about Design-for-Test methodology and tools, those of you reading are getting a fairly narrow view of the wide world of DFT. I admit it. And I believe I’ve said from the beginning that one of the reasons for this blog in the first place was to get me to peak out of my box a little - learn and explore.

So to that end, I decided to look beyond the big few EDA vendors and their test-related offerings to some of the smaller companies and the variety of different technologies beyond scan, ATPG, and BIST that are offered.

As it turns out, there is a spectrum of DFT-related products that spans all the way from RTL design-for-test tools to silicon defect diagnosis tools that analyze ATPG failures. You may recognize the latter as that which is classified as a fairly popular DFM methodology these days.

But it’s not all just EDA software. There has been, for many years, a class of ATE called DFT testers. These are testers targeted mostly for design debug, have toned-down specs, and a much smaller footprint as compared to the “big iron” ATE marketed by Advantest, Teradyne, Credence, LTX, etc.

There’s a lot to cover in that spectrum, so stay tuned. I’ll look at RTL design-for-test first, and make my way toward the back-end of the flow…

I’m going to have to learn about and work on my spam management for this site… I guess it’s good that people can find my site, and the stats are increasing every month, but I’ve got to wonder just how much of the traffic is due to these spam-bots. Just lately, it seems I’m moderating more and more comment spam. And it’s getting to the annoying point.

Time to activate a couple of Wordpress plugins to make it harder, I guess. Anybody out there have any suggestions?

Update: I installed the Askimet spam filter a few hours ago, and it’s already weeded out 3 comments (and they’re all true spam). So that’s good. John Busco also suggested a CAPTCHA, which is the name for those things where you have to type in the distorted letters. I might end up doing that if Askimet doesn’t do the job.

In my DAC and DFT - post #2, I linked to an article at Test & Measurement World, that briefly outlined a few different ‘new’ DFT technologies being pursued by the big EDA companies. One of these areas was termed volume diagnostics or defect diagnostics. This ‘new technology’, to me at least, is more DFM than DFT, but I’ve said from the beginnings of this blog that DFT has an important part to play in this new acronym.

The concept behind this is that data collected during test, especially scan test (ATPG), can be used to track down problems - in the layout. As I poke around the online information, I get the feeling that defect diagnostics refers to the ability to import test (ATPG) data into a physical design environment and locate the probable site of a defect. Volume diagnostics, I think, refers to the same thing on a larger scale - in other words going from failure analysis to yield analysis, or going from analyzing a possibly random defect to a systematic defect, that may be present due to the way the IC was designed and laid out.

This data collection is the subject of an open meeting of the STDF Fail Data Standardization group at Semicon West next week.

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Although there is little in the way of Design for Test material there, just thought I’d mention Semicon West 2007, happening in a couple of weeks (July 16-20 at Moscone Center in San Francisco). The thrust is definitely aimed at the technology of test, which, for all you front-end designers, is the place where your designs are made profitable. The focus of Semicon are extremely challenging technologies that somehow keep a half-step ahead of IC design, in order to be able to test the faster and bigger designs coming down the pike. I’ve been out of the ‘test engineering’ field for over 10 years, and I can’t believe what these people are doing!

If you look at the subjects of discussion at Semicon, it makes me wonder, beyond the obvious DFM link, why, earlier this month, Magma CEO Rajeev Madhaven suggested that DAC be combined with Semicon. Yes, there is a meeting place between Design and Manufacturing, but the enabling technologies are very different. It might be interesting for a couple of years to expose IC designers to test technology for the wow factor. But after that, the different crowds would be attending to their own interests.

Maybe Mr. Madhaven was just thinking it’s be easier to support one less show…

One of the areas of DFT development pointed out by Richard Quinnell of Test & Measurement World in his article entitled “Vendors pursue DFT strategies“, part of T&M’s DAC roundup, was test for ‘low-power designs’. Another term gaining traction for the process of coming up with these ‘low-power designs’ is ‘Power-Aware Design’. In fact Gabe Moretti is suggesting the use of its acronym, PAD. Fine. Put me on record for for coining the follow-on acronym: PAT. Power-Aware Test. We need more acronyms!

In my mind, there’s actually two facets to this: DFT in the PAD, and PAT. Catch my drift? There’s a difference between being able to actually implement a working test solution in a low-power design and implementing a solution that will yield good results and not burn up the chip.

In the first case (DFT in the PAD), there seems to be a bit of concern for what happens to your DFT effort when some of the latest power reduction techniques are employed. In fact in the article “low-power SOC design takes on new meaning” over at EDN, Ron Wilson worries that techniques such as voltage islands and power gating could complicate, if not be completely incompatible with DFT methodologies. At the least there are additional worries associated with new structures such as level shifters and isolation cells when it comes to testing the PAD.

In the second case, there’s power-aware test (PAT) or DFT - and this is different than the first case. With PAT, the focus is on test methodology and DFT features that will not over-tax the power structures on the device, causing false fails, false passes, and even worse, damaging the chip. Some DFT vendors have worked on creating ATPG vectors with optimized X-fill. Some researchers (see reference 19) have investigated techniques using this capability along with targeting subsets of faults to lower the average switching power during at-speed scan testing.

In either case, there’s quite a bit of interesting work going on in the area. Pay attention…