DFT Digest

One of the announcements from Test Week’s onslaught of test-related press releases from EDA vendors was Magma’s roll-out of Talus ATPG and Talus ATPG-X.   A couple of interesting things about this product:

1)  Its tight integration into the Talus toolset means that it is a Magma user’s tool only.  So Magma is marketing it to about a third (?) of the total available ATPG market.

2) Its both multi-threaded and distributed - which are probably both necessary given the fact that the tool is tapping into the physical database to target multiple fault models concurrently (this was Siyad’s first comment when we were discussing the announcement).

3) It uses a ’stateless broadcaster’ and compactor for test data compression, for a ~40X compression capability.  This is similar to Synopsys’ DFT MAX compression.  There are other similarities as pointed out in this post at The Tao of ASICs (amongst them, a prime example of synchronicity related to multiple fault detection using one pattern, including reordering of patterns based on fault type) .  The Tao is declaring it a “DFT Arms Race”.

Talus ATPG and ATPG-X are placed right in the sweet spot of current ATPG development - links to the physical database and detection of multiple fault types.  We’ll be interested to see how this plays out.

Coming up later this week we’ll discuss more of last week’s announcements.

Well, like I mentioned in a recent post, DFT Digest did have a mole at ITC - I wasn’t there (as I never get tired of mentioning - what a complainer!), but my partner Siyad Ma was there. He shared some of his thoughts in the comments section of my last post. To him, attendance seemed to be down this year, which translates to lots of swag left over (sounds like there was some cool give-aways, though: Cadence gave away Nintendo Wii’s, Mentor gave away iPhones, and Magma gave away an iPod Touch).

From the technical sessions, Siyad made mention of a few papers:

“On-chip Timing Uncertainty Measurements on IBM Microprocessors,” R. Franch et. al.. They described a very cool on-chip measurement macro block (SKITTER) that can measure skew and jitter. One of the coolest thing is that this macro can run in a scope mode, so you can see the edges being modulated with switching activity inside the chip.

“X-Canceling MISR - An X-tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR,” N. Touba. Prof. Touba showed a way to remove unknowns in a MISR by further XOR different bits of the MISR, effectively cancelling the effect of the unknowns.

“Testing of Vega2, a Chip Multi-Processor with Spare Processors,” S. Makar, et. al. Dr. Makar described the DFT methodology used to test a chip with 48 processor cores plus a few spare cores, which can be used to replace defective cores, thus enhancing yield.

The corporate announcements this week were fairly interesting. There’s links to all the ones I saw on the DFT News page. I’ve not had time to dig into all of them, but I’d like to, as time permits. Synopsys led the pack in quantity with three design/test-related press releases this week: ATPG for small-delay defects, automation of power-management aware test insertion, and a test & yield data flow tool, called Odyssey. Mentor rolled out an improved test compression architecture to extend the amount of compression possible for a chip under test, to accommodate the growing number of patterns needed to test for a growing number of fault types. Cadence had no product releases to offer, but did announce some customer successes.

Magma joined the fray with the introduction of their ATPG and ATPG compression tools. Same as last year, they partnered with other companies (last year with Genesys TestWare and Mentor, among others, and this year with Inovys and Source III) in a variety of announcements.

Another interesting new development this year was DeFacto Technologies, a French startup dedicated to povide DFT at RTL (Register Transfer Level). DeFacto’s tool analyzes your HDL code, decides what test structures to use, and inserts them into your code. They do scan now, and are currently planning a BIST implementation.

On the board test front, Asset Intertech announced support for embedded instrumentation based on Intel’s IBIST for high-speed chip to chip communication. Intellitech, also in the JTAG arena announced a tester that can concurrently test up 32 JTAG ports on PCBs with ARM processors.

Well that was a link fest… enough for today, but we’ll keep on discussing these things in the coming days and weeks. Add your comments below, at DFT Forum, or e-mail me at jford@dftdigest.com.

TGIF Folks! Some of you are still milling about Santa Clara, possibly attending one of the workshops. Others have packed it in and gone back to work. And me, I’m still chained to this workstation… so if you went to ITC, it was, by default, better for you than for me!

There are three workshops this year: DFM&Y (Design for Manufacturability and Yield), which is the more “design” part of test, DBT (Defect-based Test), which is more “test”, and ATE Vision 2020, where people will either be talking about test in the year 2020 or sharpening their vision (to 20/20) of the future of test in general, depending upon who you talk to. Something for everyone here.

Speaking of DFM, panel 4 on Wednesday explored Test’s role in DFM (Does Test Have a Greater Role to Play in the DFM Process?). Tets Maniwa wrote about it in an article at EE Times here. This is a subject that I’ve wondered about in a few different posts when DFT Digest first started. Just do a search for DFM. And you’ll see the subject has come up. It’s good to see DFM being discussed at ITC.

I’ve gotten some feedback on the conference this week, so I’ll be posting regularly to discuss some the more interesting papers, panels and addresses. I invite all you readers to get me your feedback, either by commenting here, or e-mail me at jford@dftdigest.com!

It’s Thursday morning, third day of the International Test Conference, last day of the technical paper sessions (Workshops start tomorrow). If you’re an ITC attendee, you may be hung over from too much cheese at the wine and cheese event - any good scuttlebutt? Do tell…

Yesterday, the reports (here and here) from the first day speeches hit the web. Most covered the keynote speech, given by Gadi Singer of Intel, who talked about the massive increase in IC complexity. Moore’s law, alive and well. He stated Mips/cubic feet has increased 100x every 10 years. Hmmm… do I smell a new law? ‘Singer’s Law’? Moore has been trying to disavow his law for years - these Intel guy’s and their laws…

DFT Digest also had our man at the keynote. Siyad adds this about what Mr. Singer had to say: “He mentioned that the main challenges were from 4 directions: complexity of the new designs, ever increasing of performance while keeping power constant, complexity of nanometer technologies, and pressures of time-to-market”.

Singer said that the laws of increasing complexity were not going to be broken in the foreseeable future. Part of the reason that this is true is that design process have moved increasingly into IP, with more modularity, and more reuse. Test and Verification, however, have not kept with rapid change, so he challanged the audience to come up with new solutions, including more up-front planning, modularity and adaptive methods to keep up with the rapid pace.

Speaking of adaptive methods, Ken Butler also gave his address on adaptive test on Tuesday. This article covered that talk, and I’ll blog on on it later, because I find it very interesting.

Today’s International Test Conference promises a full day of technical paper presentations, a lecture series, five panel discussions and at the end of the day, because you really should be exhausted after all that - the Wine and Cheese reception.

Today’s topics include test power issues, ATPG and delay test, functional and outlier test, advances in SOPC test, boundary scan, and wafer probing. A cornucopia of interesting topics.

Al Crouch will be giving the invited address at 1:15PM, called The Need for Standard and Efficient Interconnection and Access of Embedded-everything, targeted toward his work on the embedded JTAG initiative called IJTAG (IEEE P1687). I seriously hate to be missing this.

I missed a couple of items about yesterday - first, Ben Bennetts gave his invited address, a DFT retrospective. I’ll be anxious to see how that went. Also, the Magma lunch was yesterday - they rolled out their new ATPG products, and had invited Dr. Mohammad Tehranipoor to give a talk. If anybody reading out there attended these, drop me a message, and tell me what you thought!