DFT Digest

After two days of day-long tutorials, the International Test Conference has officially begun - the keynote address has just ended as I write this - sadly, I’m stuck at my workstation this week - so I’m depending upon you readers to feed me info and your impressions of the interesting goings-on…  Siyad will be dropping in, and I’m sure he’ll be adding his insights.

As far as the rest of the day is concerned, don’t miss Ken Butler’s invited address Pinning Down This Elusive Thing Called “Adaptive Test”.  It starts at 1:15PM.

The technical sessions start  at 2PM, and if I were there, I’d be attending session 4, New SerDes Test Techniques, and then bouncing back and forth between sessions 5 and 8 SOC Test and Breaking the 10-Gb/s Barrier - but that’s just my interest - what are yours?  Let me know.

Also, there are a lot of press releases coming through, and I’m posting them as they come, on the DFT News page.

Hello from hot and smoky southern California - fires all around us (wheeze).

Up north, ITC 2007 has begun, and the second day of tutorials is half-over, and companies involved in creating products for test and design are queuing up the PR to be released throughout the week. See the latest news coming out, go to the DFT News page of the Digest.

If you happen to be there, and see something interesting that you’d like to discuss, go to the DFT Forum, register, and post it there for discussion. We’ve updated the forum to have a similar look and feel to DFT Digest, just so you know you’ve arrived…

If you have any suggestions for either site, please e-mail me at jford@dftdigest.com

As I mentioned in my last post, I asked a few friends and acquaintances what they were looking forward to at ITC this year. My next respondent is Mohammad Tehranipoor of University of Connecticut.

Mohammad is, as he mentions below, the Program Chair of the workshop titled DBT: IEEE Workshop on Current- and Defect-Based Testing. I think this topic will be promising to a long time to come. Somehow we’re going to have evolve our fault models to maintain and improve test quality.

Dr. Tehranipoor answered each of my questions specifically, so you, the reader can make your judgment as to whether the questions were good or bad. Whatever the case, the answers are good. Remember, the text in italics are my thoughts not his.

1) What do you see as the most compelling/interesting directions of the technical content this year?
The focus of this year’s ITC is on facing nanometer technology test challenges. I look forward to technical sessions on DFT/DFM, yield and adaptive tests. Among traditional tracks, I look forward to delay testing papers. Among keynote addresses, I would like to see Ken Butler’s talk on Pinning Down This Elusive Thing Called “Adaptive Test”.

2) How do these directions compare with last year?
Last year there were more focus on getting more out of test and more focus on test quality, yield, test compression and diagnosis.

3) Looking forward to any interesting fringe meetings/activities?
Magma’s luncheon meeting — Magma is releasing new physically aware ATPG
DBT workshop because of it’s excellent program — Note: I’m DBT Program chair

Ahh, the new Magma tool. I’m really interested for the details to come out on this. Actually, Dr. Tehranipoor will be a featured guest at the Magma lunch, giving a talk to “discuss the need to bring layout, timing and variation information into DFT/ATPG”. Count me bought in on that notion…

4) If there was any event that you would tell people not to miss, what would it be?
Besides DBT, I’d say invited addresses.

I’d like to thank Mohammad for contributing his answers and giving us all another view of what’s going on at ITC!

The International Test Conference starts next week, and as a lead-up to the conference, I’ve been asking some friends and acquaintances in the industry to tell what they’re looking forward to seeing and learning at ITC this year.

The first person to heed the call was Ken Butler, TI Fellow at Texas Instruments in Dallas, TX. Ken will be giving an invited address on Tuesday, Oct. 23, 1:15-1:45, titled Pinning Down This Elusive Thing Called “Adaptive Test”. Being as humble as he is, Ken did not mention this in his “must see” list, but other respondents did, so I mention it here. According to Janusz Rajski, ITC program chair, adaptive test “is an approach where you want to figure out the most frequent and prevailing ways in which devices fail [in order to] develop your tests to maximize the coverage of those most likely defects”.  If I were going, I’d be there!

Ken is not on the program committee this year and hasn’t seen the papers beforehand, but he did say the following about the lecture series:

“Rob Aitken took over the lecture series this year and he is well-connected throughout the industry so I expect the lecture series to be particularly good this year. Al Crouch is giving one of the invited talks and he’s always entertaining, so that one probably makes the “not to miss” list. I’m sure Gadi Singer’s keynote will be great as well. Ben Bennetts has been around for a long time and now he’s retiring, and he’s giving a talk about the changes in the industry. That should be good.”

As far as what the hot topics are this year, Ken says, “Small delay testing is getting hot. So is diagnosis. Adaptive test has been getting hot for the last couple of years.”

In addition, Ken mentioned several fringe activities going on that could be interesting (the comments below in italics are my own - not Ken’s):

STC University Working Group Meeting, Monday, Oct 22 - Semiconductor Test Consortium: I’ve mentioned this group in the Digest before; interesting subject on it’s own. Is working actively with universities to improve semi test curriculum.

Synopsys SIG (Special Interest Group) event, Monday, Oct 22 - Featuring speakers from ARM and ST, singing praises to Synopsys’ test solutions.

Mentor’s DFT X-press Rollout, Tuesday, Oct 23 - Presentation of new TestKompress technology enabling >>100x compression (including, hopefully, why you need it).

TSSI Panel, Wednesday, Oct 24 - Title: Test Engineering in the 21st Century: The Role of STIL and Pre-Silicon Test Validation in Cycle Time Reduction.

Joint GSRC/C2S2 Test SIG Meeting, Monday, Oct 22 - An afternoon of potentially very interesting short talks on many areas of test such as: Digitally-Assisted Analog Test, Parametric Modeling Framework for Analog Test, Progress in On-Chip Microwave /Millimeterwave IC Test.

Thanks to Ken for taking time to give us some additional insight to this year’s ITC!

Remember way back, this time last year, there were rumors about that Magma had abandoned their design-for-test tools?  First, there was a post over at DeepChip,  about the cancellation of their test program.  Less than a week later, Richard Goering at EE Times wrote an article stating that, according to Magma marketing folk, Magma did indeed drop out of the BIST market, but was working on an ATPG offering (which was “in alpha stage”).

That was shortly before ITC last year, and when I asked about it at their booth, people looked at me as if they didn’t know what I was talking about (I guess they don’t talk about these things to just anybody - that’s OK).

Well, today, Magma announced  Talus ATPG, and Talus ATPG-X, for ATPG and test compression, which are integrated into their physical suite, and claimed to be the only truly physically aware ATPG implementation.   Other claims include multi-threaded operation, and concurrent targeting of multiple fault models.  The press release included comments from two companies that have seen the product: IDT and Comtech AHA.

Anybody else out there seen the product?  Let me know what you think.  Is ATPG becoming a commodity (everyone offers it)?