DFT Digest

Last week, John Cooley published the results of his 2008 DeepChip Synopsys Survey, and of course I went straight to item #6, entitled “Synopsys DFT Compiler/TetraMAX vs. Mentor DFT Advisor/FastScan“. There are some surprises and head scratchers:

• By John’s count, Synopsys DFT Compiler only has 50% of the scan insertion market. Gary Smith believes it’s more like 78%.
• According to his respondents, Synopsys TetraMAX is used twice as much as Mentor FastScan! Gary Smith’s numbers say the exact opposite.

Even John wonders, “…according to Gary, my DFT Compiler percentage is too low and my TetraMAX percentage is too high. Why that is, I don’t know“.

Well, a couple things occurred to me:

First, I believe John’s audience (and by extention, survey respondents) is skewed in a couple of ways:

• It’s ESNUG (The S stands for Synopsys), so mostly Synopsys users responded.
• It’s my belief that the Deep Chip audience are mostly designers, who are famous for not knowing exactly what’s going on in the DFT world, even on their own chips.

Second, related to my characterization of chip designers’ ignorance of their own DFT methodology, is that many don’t realize that the tools don’t stack up one for one - in other words, If I use Synopsys DFT MAX (compression tool) and Synopsys TetraMAX (ATPG tool), it’s not the same as using Mentor TestKompress (compression tool) and Mentor FastScan (ATPG tool). That’s because FastScan comes as a part of TestKompress. The Synopsys tools are separate. So when someone reports using TestKompress, you must put a mark in both The TestKompress and FastScan columns in order to make an apples-to-apples comparison.

So what do I think? Well, I believe Gary Smith’s DFT Compiler number. I think fewer and fewer people are inserting scan after synthesis is complete, most now compile scan-ready as part of their synthesis flow. Scan stitching can be done also with the place & route tool in some cases. So about 80% seems right.

On the other hand, I don’t believe either Gary or John about the ATPG tool balance. I think it’s closer than either of them say, but with TetraMAX slightly in the lead.  There are many decision makers out there today putting together cost-driven tool bundles - and will go Synopsys because they’ve got the whole flow integrated.

I have no hard data to support any of my claims, but it’s the sense I get when I talk to people…

No really, no kidding - just joking.

Anyway, I wanted to pass along a reminder from Louis Ungar of A.T.E Solutions that TMAG (Testability Management Action Group) will be holding general meeting #3, on April 1, 2008 at 11:30PDT (US Pacific Daylight Time), in conjunction with the APEX conference in Las Vegas, NV. There is a conference call number set up as well as a Webex. See their website for details.

TMAG is a “grass roots organization made up of test professionals who believe that success for Testability in general, and Design for Testability (DFT) in particular, requires the involvement and the support of management at all levels” [from their website].

They have established a number of committees within the group, addressing subjects such as test economics, tools, methodology and management. Take a look, and get involved! The members come from everywhere in the industry - and there’s not an april fool among them!

Very funny - EDN’s blogger Margery Conner posts that today is ‘Pi’ day (March 14th, a.k.a 3/14, 3.14, pi).

Editor Rick Nelson points out that they can’t observe Pi day in Europe, since they write their dates differently (14/3/2008).

Then of course, someone has to say that they guess that makes it American Pi day - hee hee!

Good day DFT folk - just a reminder, DATE 2008 started today. For those of you readers who are lucky enough to be in Munich this week for the event: What are you looking for? What sessions, and/or events do you have your eye on?

One person there this week is JL Gray of Verilab, and author of the blog Cool Verification (there’s a link to his blog in my blogroll over in the right-hand sidebar). You can see his initial post regarding this year’s DATE here.

JL solicited suggestions for interesting session or events from his verification readers. I had to chime in from the perspective of a test guy. Here’s what I said:

For Tuesday, First, I’d go to session 1.5, Advances in BIST for mixed-signal devices, and see if I could make it through all the math without a brain implosion. It’s an area of test that needs attention.

Then I’d stagger over to session 2.5, Advances in SoC Test, where I’d be a bit more comfortable, because that’s where I live - very concerned about test data volume.

Wednesday, I’d attend Session 6.5, the Hot Topic: Test Challenges for Low Power Devices. I think this is the top test issue for 2008.

Beyond that, I’m pretty interested in any of the musings surrounding the next couple of technology nodes (45nm, 22nm). I’ll be living through them in the next couple of years. Exciting times… the variability dimension in chip design is a new frontier, I think.

Low-power test design is also a big interest for me - so any of those papers would attract my attention.

So what do you all think? What interests you? Again, if any of you are in attendance, I’d really appreciate an update from you.

Bis Später!!

I was reading Peggy Aycinena’s DVCON post at EDACafe this past week, and ran across a couple of thought provoking (at least for me) paragraphs. Ms. Aycinena was describing the Wednesday keynote speech given by Wally Rhines of Mentor. He opened his talk with a discussion of DFT. I’m reproducing most of the DFT part, and only a portion of his verification discussion, for brevity:

…He said on-chip complexity forced folks to search for better ways to test over the years. Bigger and faster computers had helped, as had testing for stuck-at faults, but the number of transition faults still got bigger. Test engineers beat that stuff back, Rhines said, by shifting to scan-based test, by introducing ATPG, BIST, and ordered-test patterns, and had increased test efficiencies by up to 10x. But it wasn’t enough because even though the cost of components came down, the cost of test did not.

Then in 2001, Rhines said Mentor’s DFT guru Janus Rajski came up with a new approach based on the theory that folks should stop testing what they’ve already tested. Rhines said implementation of the algorithms behind on Rajski’s theory, in combination with test-data compression, has increased test capability 100x and will increase that capability 1000x in the next 5 years. He concluded, “We moved from a mode where we added more cycles of test, to a mode where we added more test per cycle.

Rhines moved on to verification and reiterated what everyone knows – except those who’ve been on a different planet for the least 10 years – verification costs more than design, and that’s way, way too much. [snip - and Rhines says] “I believe that there’s something out there that will do for verification what test-data compression did for test,

So how about that? For so many years, test borrowed from verification, in that functional patterns originally used for verification were re-targeted to the ATE to screen parts. Advances in DFT methodology, from necessity, made huge gains in efficiency by looking at the problem structurally. Now verification, painfully expensive and time consuming, could benefit from the same kind of innovation.

Any ideas out there? There’s money to be made….