DFT Digest

For most of the average joes attending the Design Automation Conference, it’s a time to walk the exhibit floor, witness demos of the latest EDA gear, take in some interesting technical sessions, and maybe attend a party or reception.

But if you dig around the DAC website, you’ll see a link to something called “Collocated Events“. I guess, as is the case with any large conference, the DAC event makes it convenient for other events to happen around the same time and place: various meetings, symposia, even full conferences.

The one link to a collocated event that caught my eye, being a Design for Test guy, is the Global STC Conference, presented by the Semiconductor Test Consortium, taking place just before DAC, June 4-6, in San Diego.

STC is probably most known for promoting the OPENSTAR intiative (open architecture for ATE). They also work on standards for docking interfaces and probe cards, all very test-floor centric activities, not normally the concern of designers. The agenda is dominated by those issues, but on June 5th, the second day of the conference, there are couple of sessions that piqued my interest: “Cooperation Between EDA and ATE: Now More Important Than Ever“, presented by Ed Malloy of Cadence, and “Design for Test - Small Price to Pay on Silicon for High Product Quality“, by Prasad Mantri of Sun.

Hey I have an idea! How about selling conference sessions a la carte? Or in mix-and-match packages (”go to any 10 technical sessions - any conference or symposium of your choice - for only $249!”). Naahh… probably too much travel. But it sounds better sometimes than purchasing a complete conference pass for the 2 or 3 really interesting sessions…

Just a short one - about a month ago, the 2008 Southwest DFT Conference was held in Austin, TX. I blogged about it here. Since I didn’t get to go, I just recently checked back to see if SiliconAid had posted highlights on it’s website - and they’re there, complete with pictures of all the happy DFT’ers and links to some of the presentations. Go check it out! Here’s the link

The conference is held every year by the folks at SiliconAid Solutions, and sponsored by EDA vendors Cadence, Mentor and Synopsys. SiliconAid provides DFT consulting services and offers a family of JTAG-related products.

One more thing: as an update to yesterday’s ‘who’s at DAC’ post, I did miss Virage Logic - they offer DFT solutions for their memories. Also TSSI, the company that created TDS (Test Design System) ATE vector translation software.

This week, I’ll try to pass along Design-for-Test related DAC news as it comes along…

First, it was announced today that the standards organization Accellera has selected Bruce Cory, a DFT manager at NVIDIA, to receive the 5th annual Technical Excellence Award, for leading the effort to bring the Open Compression Interface (OCI) to be approved by the Accellera membership, and continuing the effort to pass it as an IEEE standard (IEEE 1450.6.1, which I guess is an extension to the CTL standard).

The OCI standard will be an important step in establishing tool independence with regard to test data compression and diagnosis, while still protecting EDA vendor’s compression IP. Currently, once test compression IP from a certain vendor is incorporated into a design, ATPG tools from the same company must be used, as well as any other tool down the line (yield analysis, for example) that hopes to use ATPG data. This can get particularly problematic, especially in manufacturing and test environments that would have to support as many tool flows as there are test compression schemes.

Also today,  LogicVision announced the Dragonfly Test Platform, which will be demonstrated at DAC.  The new tool seems to be  an integration of existing, and in some cases improved versions of LogicVision’s embedded test tools addressing memory BIST and logic BIST, as well as debug and analysis tools such as Silicon Insight and Yield insight.

Earlier this month Genesys Testware announced announced yet another Design-for-X tool: Design-for-Leakage-Test (DFLT).  This is actually a feature added to their Hierarchical DFT tool, HiertestMaker, and addresses problems due to lack of testability around power-aware design structures, such as “power switches, and isolations gates”, and I assume level-shifters.  Here’s the press release.  Someone over at Genesys needs to work on their website: you may notice if you go to their homepage, the latest news is from ITC 2006, and the upcoming event is DAC 2007

Winterlogic, maker of the fault simulation tool Z01X will be exhibiting at DAC for the first time.

SynTest will also be exhibiting - stop by and congratulate L.T. Wang for being elected IEEE fellow earlier this year

Nothing test-related for Synopsys, and this is not necessarily DAC-related, but I have to brag that Synopsys has added a link to this blog on their Galaxy DFT page.  Mentor, Cadence?   Hello? 

The Design Automation Conference is just around the corner. DAC’s not usually a conference that commands much interest with regard to DFT… I recently wrote a blog post complaining of that fact, but never posted it (I like to let posts like that simmer for awhile, and many times, a re-reading of them will expose them as pathetic/worthless, and they never hit the internet). ITC is really the place for our kind of fare.

However, as long as DAC is local enough (for me, that’s Anaheim or San Diego), I like to go for the free day, skulk about the booths for anything interesting, collect schwag, try to run into as many old acquaintances as possible, and maybe meet someone new.

This year, there’s something different that may or may not happen, but the fact that it’s actually being considered is a sign of the times: a “Birds of a Feather” session featuring EDA bloggers. It’s being organized chiefly by JL Gray of Cool Verification, who really has the most traction as an EDA blogger - along with a few others that have been willing to help out. If 10 bloggers commit to showing up, a room can be reserved, and a discussion will take place. If not, the few who’ve committed can go “grab a beer and have some ad hoc discussions”. Either option is good with me. But exposing the online community to the greater EDA industry can only be a good thing in my eyes, so I’m encouraging anyone out there who has interest in participating to speak up and show up.

Here’s to making new acquaintances this year at DAC…

System Verilog was signed off as a standard by IEEE in late 2005. In the 2-1/2 years since, front-end design tools for synthesis and verification have been making significant strides in support of the standard - not without limitations and missteps - but the effort is there. Progress has been made. So what of the DFT tools? Well, so far - in my experience - it ain’t happening.

The first thing I hear the peanut gallery saying is, “So what? ATPG tools read synthesized netlists, and they’re almost always structural Verilog anyway”! True, for the most part. But how about the situation where you’ve got a mixed SoC where the top level is not synthesized? Designers, when given the chance, will take advantage of the shortcuts available in the newer incarnations of the Verilog language (both 2001 and System Verilog). So the DFT engineer is forced to retrofit the top-level modules to old Verilog.

OK - no big deal… right?

But what about other kinds of DFT tools? memory BIST tools? Boundary scan tools? In a typical flow, these tools provide efficient implementation of Design for Test by reading the design RTL, integrating the test structures into the code, and outputting the augmented RTL, ready for synthesis. So what’s a DFT engineer to do when the design team decides to transition to System Verilog? If these tools aren’t supporting System Verilog, the DFT engineer (or designer) is in for more manual work.

So what is the typical response of the DFT vendor when asked about the lag? “Not enough customer demand”. So does that mean the uptake of System Verilog is not as swift as reported?

What’s your experience?