DFT Digest

You are browsing the archives of 2008 August.

JTAG Technologies supports wide range of Freescale controllers with embedded Flash
Eindhoven, September 1, 2008 - JTAG Technologies, a leading provider of IEEE Std. 1149.x boundary-scan solutions for testing and programming printed circuit boards, now offers a family of programming tools for a large number of Freescale Semiconductor controllers with on-chip flash memory. The programmers all [...]

August 26, 2008 - ASSET assumes a leadership position as one of the founding members of iNEMI’s boundary scan (JTAG) adoption initiative
Richardson, TX (August 26, 2008) - ASSET® InterTech (www.asset-intertech.com), the leading supplier of open tools for embedded instrumentation, recently became a founding member of the International Electronics Manufacturing Initiative’s (iNEMI) boundary scan [...]

System on Chip design involves gathering functions from various sources: different teams, different vendors, doesn’t matter - there’s never enough documentation. System on Chip test, especially as increasing amounts of functionality is embedded, can become an intractable problem very quickly.

Let me hear you say yeah!

Karen Bartleson over at her blog, The Standards Game, issued an invitation to all who care*, to become a part of the balloting process for the IEEE P1450.6.1, “Standard for Describing On-Chip Scan Compression”, or Open Compression Interface. Karen has a short explanation of the idea behind the standard, and I’ve blogged about it here before. It was ratified by Accellera in October of 2006.