About This Site
DFT Digest is a weblog about electronics Design-for-Test, maintained by John Ford and Siyad Ma (see below). The purpose of the blog is to discuss state-of-the-art DFT methods, technologies and best-practices, with the ultimate aim of better understanding design for test, hopefully through the increased participation of the greater DFT community and, heck why not? Maybe even the design community as a whole.
What can you expect to see discussed here? A variety of musings inspired by my own DFT-related trials and tribulations, invitations to discuss new DFT techniques (or different applications of old techniques), a sprinkling of DFT-related news items that pop up as time goes on, and anything else I feel would be interesting to the DFT engineering community as a whole.
We can talk about shrinking geometries: what is being experienced at 90nm and anticipated for 65nm, 45nm? What techniques are more important? Less important? What about pushing DFT solutions toward the front-end of the design process (RTL)? How does low power design affect design for test? How much of your verification suite is being ported to the ATE, and to what end?
The intended audience is not just DFT engineers, to whom I’d be “preaching to the choir”, but to all those involved in the design of ICs That might be interested in the value and techniques of Design-for-Test. Therefore, the content of this website aims to be educational as well as exploratory.
DFT Digest aims to provide a vendor-agnostic environment that concentrates on methods and industry best practices. For sure, there should be discussions of this tool vs. that with regard to specific issues, but this is not a “hit-blog”. personally, I’m not interested in becoming a gadfly or a shill, for that matter, for anybody. The articles will be written by me (or perhaps a willing contributor at some point down the line), and I do not work for a tool vendor.
And if it eases any concerns maintained by the officers of the company I work for, I’ve read the confidentiality guidelines, and intend to exercise good judgement. My purpose here is to discuss the general topics and best practices of design-for-test and related sub-specialties in the implementation of nanometer scale ICs.
About Us: Hi! My name is John Ford, and I’ve been writing this blog for the last 1-1/2 years. Today I welcome a co-conspirator, Siyad Ma. Following is a bit about both of us.
John Ford
John’s been working in the semiconductor industry for almost 25 years (as a point of reference for you chippies, that would be since 3-micron lithography was state-of-the-art). He started as a test engineer at Western Digital Corporation, and has since worked in various engineering capacities: IC test (digital and mixed-signal), DFT, verification, and some design automation. Variety is the spice of life.The bulk of John’s career has been in Southern California, for WDC as well as companies such as Silicon Systems, and Texas Instruments and Freescale. He is currently stationed in Irvine CA, working for a communications IC startup, and lives with his wife and daughter in Aliso Viejo, CA.
Siyad Ma
Siyad has been in the DFT industry since graduating from the Center of Reliable Computing at Stanford University in 1995. He was part of the DFT team for the AMD-K6 product family, and architected and implemented DFT structures for Chameleon Systems Reconfigurable SOC, Zettacom’s networking ICs, and IDT’s PCI Express switches. He currently works at Cisco Systems in San Jose.
Siyad has been an active member of the Pacific Northwest Test (BAST) Workshop for the last decade, serving as General Chair for BAST 2006 and BAST 2007.
Outside of DFT, Siyad enjoys basketball, photography and travelling. You can view his travel photos at (http://www.siyadma.org). He lives with his wife and three children in Palo Alto, California.
Keywords (Yes, these are what I want to talk about): Design-for-Test, DFT, DFT best practices, Semiconductor test, ATE, BIST, memory BIST, logic BIST, Scan, scan-stitching, lockup latches, clock skew, ATPG, at-speed test, fault coverage, stuck-at fault, transition fault, delay fault, Test compression, DFM, Design-for-manufacturing, nanometer design.It’s all good…(updated 11/09/2007)
