DFT Digest

More than once, I’ve had requests to address analog (or analogue, if you’re a Brit) testability in this blog. I barely touched on it back in December of last year, in this post. I briefly mentioned some things I’d dealt with many years ago. Thinking about it today, it sure doesn’t seem like the EDA industry has come too far since then, with respect to providing tools for automating this kind of DFT. So it’s fair to say that mixed-signal design-for-test is really an ad-hoc process most all the time.

Other things that haven’t changed much are the types of circuits needing test: Amplifiers, filters, PLLs, ADCs, DACs, bias generators, regulators. Of course there are many more, but in the world of SoCs, those are the usual suspects. Agreed? If you’re involved with communications systems, you’d probably have to add a SerDes to that. Most of these are not pure analog, but actually mixed-signal, a combination of digital and analog. The digital circuitry, in these cases, is not normally structurally testable logic, but carefully crafted custom cells. And that’s just another facet of planning testability for mixed-signal circuitry…

The basic objective of analog DFT is the same as in digital cases. You have to maximize controllability and observability. Somehow, if there is a defect in your circuit, it must be possible for the effects of that defect to be propagated to some observation point. The observation point doesn’t have to be external; if you can figure out how to test your circuit internally, it usually saves test time. There are some products on the market that help in this regard. I’ll mention some as we go along.

In the near future, I’ll go through some of the different kinds of analog circuitry I’ve had to deal with, and some ideas for enhancing the testability. If you’re reading - send in your ideas. Educate the community!