DFT Digest

I’m just going to have to accept the fact that when I go back and read some of my posts, in retrospect they will seem like pointless rambling – and that I’ll try to go back and bandaid them only to make them worse. It seems that could happen more often in this type of forum, the blog, especially because we’re discussing something as involved as design for test.

I felt that way even as I posted my last post on why we do DFT at all. The answer was that it has to do with test economics. But my post only felt like qualitative poking and prodding at something much more substantial than the post would lead one to believe. Engineers do research and publish papers on test economics. It’s important and becoming more so, and I think it’s a must for every electronics engineer considering a new test feature to understand the subject.

I don’t believe I’ve understood test economics well enough myself over the years. So I did some reading. One of the books I’ve picked up in the last year is Essentials of Electronic Testing, for Digital Memory & Mixed-Signal VLSI Circuits, by Bushnell and Agrawal. It has a pretty nice section on test economics. One of the things I like about this book is that it has an extensive bibliography (almost 750 references) that it consistently points to throughout each chapter, if the reader wishes to drill deeper into any given subject.

One of my take aways from this particular section was the component of the overall cost of test that is yield related. The classic equation for yield as a function of chip area (A), defect density (d, sometimes called “d-zero”), and clustering factor (a) is as follows:

Y = (1 + Ad/a)^(-a)

(As a side note, here’s a limitation of blogging software: no integrated support for Greek characters – a is supposed to be the character ‘alpha’).

This equation is referred to as the process yield. With no consideration for test, one can see that since the exponent is negative, that an increase of the die area A or inherent process defect density d will cause the yield Y to go down. The clustering factor has to do with how defects are grouped across the wafer. The larger this factor, the more evenly distributed the defects are across the wafer. So, it turns out that more clustering is good for yield.

A modified equation is given when a test is added:

Y = (1 + TAd/a)^(-a),

where T is a test coverage number between 0 and 1. Given where in the equation T is, one can see that the yield also goes down as the test coverage goes up. With 100% test coverage, your yield is equivalent to  the process yield.

Bushnell and Agrawal give an example of how to use this equation to help evaluate the cost/benefit trade-off of an added test feature. In the example, only the process yield equation was used to demonstrate that adding an extra 10% to the area of the die to accomodate a test feature, for a given defect density and clustering factor, reduced the process yield by 2%.

Well what if that test feature was scan? Well we might be able to use the second equation to see the cost/benefit trade-off. The original example had a 8mm square die (0.64 square cm), a 1.25 defect density and 0.5 clustering factor. Well, if we use 75% as a very impressive functional test vector coverage (as I discussed in my last post), 95% as a lackluster coverage for a scan implementation, and the added 10% area hit for scan, the difference looks like this:

1) No scan, functional test only

Y = (1 + 0.64 * 1.25 / 0.5)^(-0.5) = 0.62

Y = (1 +  0.75 * 0.64 * 1.25 / 0.5)^(-0.5) = 0.67

2) Scan implemented, ATPG

Y = (1 + 1.1 * 0.64 * 1.25 / 0.5)^(-0.5) = 0.60

Y = (1 +  0.95 * 1.1 * 0.64 * 1.25 / 0.5)^(-0.5) = 0.61

So the difference is big: In the first case we’re shipping 5% (0.67-0.62)  bad parts – test escapes!  This number is commonly espressed as defective parts per million, or DPPM – in this case 50,000 DPPM!

In the second case, a mediocre scan implementation (a well-scanned device would get 99%+ fault coverage) only gives up 1% or 10,000 DPPM.  I say only, but this number not very good either. In many industries, anything over 1000 DPPM is not acceptable, and a handful of industries where lives are on the line (like the automotive industry), the requirements are near zero.

Regardless, I hope this example illustrates clearly why the inclusion of  scan/ATPG in a digital circuit, even with a slightly exaggerated area hit (10%) and mediocre fault coverage is pretty much a no-brainer.

Of course, it is also pointed out in the book (which I recommend), and I’ll repeat it here: yield is but one component of the cost/benefit analysis.  There is also EDA tool costs, development time, and ATE costs, among other factors.

What other factors can you think of?