DFT Digest

I’ve been trying to put together some info about JTAG and boundary scan, but being a chip engineer, I’m having a hard time expanding my mind to the edges of the device lately. However, this item came across my e-mail this week - a free, expanded version (110 pages) of Asset Intertech’s Boundary Scan Tutorial.

You must register to get it sent to you, but it’s FREE ( from experience, I know that word FREE is a huge magnet for engineers, most especially when it precedes FOOD )

As I was at their website signing up for the book, I found, on the same page, links to some great material on boundary scan DFT from both chip and board-level perspectives, developed by Ben Bennetts. Dr. Bennetts retired this year, but his legacy lives on in this great material! Go check it out! Lot’s of information on the many facets of boundary scan ind it’s applications. I wish all EDA vendors had this type of educational content available to the public. Our DFT engineers, more often than not, are not getting this in school.

Alright Asset, I’m waiting by my mail box…