DFT Digest

So, as I was saying, I wandered around DAC for a few hours on Wednesday, and it was fairly quiet, test-wise. Anything I saw there, I saw at ITC in October:

I listened to Tom Williams of Synopsys give a very quick talk on DFT at the submicron level, which, if you blinked, or got distracted in any way, you might have missed a whole sub-topic . If you want to see some of the slides from his talk, you might be able to catch the pictures as part of Peggy A’s article. He showed the Stonehenge pictures to keep us awake. As for DFT, he talked about the limits of test-compression (a subject I still haven’t reconciled in my mind) , picking the worst case paths for transition faults, and the assertion that choosing the most power aware X-fill for ATPG is much easier given the compression architecture of DFT MAX.

Although I wasn’t able to attend, Mentor gurus presented two different test-related papers, one on a new low-power test data compressor, and one detailing an algorithm for generating patterns while considering timing constraints and exceptions.

LogicVision had a fairly low key booth highlighting their BIST solutions.

I stopped by SynTest’s booth and talked to Marketing VP Ravi Apte for a few minutes. SynTest has always been an enigma to me, partly because I live in Southern California, and they don’t have a big presence down here, partly because it’s kind of hard to get much more than datasheet level information about their tools unless you’re a customer, and partly because I’ve never met anyone that uses their tools… not the fault of SynTest – I hear they’re big in the bay area, and in the Pacific rim. If any of you out there are SynTest customers, I’d love to hear what you think of their tools. According to Mr. Apte, they’ve got a full DFT offering, except they’re much more reasonably priced. Oh yeah, and they’ve got the only viable fault simulator out there, that I know of.