Deep Chip survey results and DFT – believe John or Gary?
Last week, John Cooley published the results of his 2008 DeepChip Synopsys Survey, and of course I went straight to item #6, entitled “Synopsys DFT Compiler/TetraMAX vs. Mentor DFT Advisor/FastScan“. There are some surprises and head scratchers:
- By John’s count, Synopsys DFT Compiler only has 50% of the scan insertion market. Gary Smith believes it’s more like 78%.
- According to his respondents, Synopsys TetraMAX is used twice as much as Mentor FastScan! Gary Smith’s numbers say the exact opposite.
Even John wonders, “…according to Gary, my DFT Compiler percentage is too low and my TetraMAX percentage is too high. Why that is, I don’t know“.
Well, a couple things occurred to me:
First, I believe John’s audience (and by extention, survey respondents) is skewed in a couple of ways:
- It’s ESNUG (The S stands for Synopsys), so mostly Synopsys users responded.
- It’s my belief that the Deep Chip audience are mostly designers, who are famous for not knowing exactly what’s going on in the DFT world, even on their own chips.
Second, related to my characterization of chip designers’ ignorance of their own DFT methodology, is that many don’t realize that the tools don’t stack up one for one – in other words, If I use Synopsys DFT MAX (compression tool) and Synopsys TetraMAX (ATPG tool), it’s not the same as using Mentor TestKompress (compression tool) and Mentor FastScan (ATPG tool). That’s because FastScan comes as a part of TestKompress. The Synopsys tools are separate. So when someone reports using TestKompress, you must put a mark in both The TestKompress and FastScan columns in order to make an apples-to-apples comparison.
So what do I think? Well, I believe Gary Smith’s DFT Compiler number. I think fewer and fewer people are inserting scan after synthesis is complete, most now compile scan-ready as part of their synthesis flow. Scan stitching can be done also with the place & route tool in some cases. So about 80% seems right.
On the other hand, I don’t believe either Gary or John about the ATPG tool balance. I think it’s closer than either of them say, but with TetraMAX slightly in the lead. There are many decision makers out there today putting together cost-driven tool bundles – and will go Synopsys because they’ve got the whole flow integrated.
I have no hard data to support any of my claims, but it’s the sense I get when I talk to people…
Stumble It!
You’ve actually revealed a very interesting aspect of a limited media society. Your view of Deep chip is correct. It’s a designer-centric world and a bit skewed to the Synopsys universe. So everything in it is going to be affected. It’s a great example of the observer effect in that the observer changes the outcome simply by observing it.
The semiconductor world, from an economic perspective, is consolidating, but from a market perspective it is fragmenting. There is less understanding, less perspective, and less objectivity then ever. None of the vendors are listening to the customer and the customer doesn’t believe the vendor.
’tis true… I have my own biases, based mostly on familiarity. It’s a comfort-zone thing. I call this a Design-for-Test blog, but I know darn well that I cover a fraction of the issues – all due to the fact that I’ve work in a small corner of the industry.
Thanks for reading Lou!
JMF
Personally, I would expect DFT Compiler users to abound due to the fact that Design Compiler still owns the market on synthesis. It’s just much easier to do “compile -scan” vs. writing out a netlist, reading it into DFT Advisor, inserting scan, writing out, reading in, reapplying constraints.
As for DFTMax and TestKompress, my client has used both and they seem on par. Again, the integration of DFTMax with Design Compiler makes for a much easier flow, as it does with boundary scan synthesis.
The hole that Synopsys has in the test flow is in MBIST and LBIST. Synopsys was almost in beta with an MBIST tool several years ago and dropped it because they felt they could not compete with free MBIST solutions from the memory vendors (ARM, Virage). LBIST has always been somewhat of a niche product (mostly mil-aero) but is now getting wider acceptance. For customers that need either or both of these, they have only the choice of using Mentor.
I don’t know much about the Cadence test tools, other than they were acquired in some fashion from IBM. Does anyone know if they are worth considering if you are using a Cadence flow (e.g. RTL Compiler)?
Hey John,
According to our DFT Forum survey ( http://forum.design-for-test.com/viewtopic.php?t=14 ),
Fastscan/Tetramax/Encounter Test shares look like 50/20/30.
I know that our results is definitely skewed (plus our sample size is too small), but what it tells me is that the folks who John Cooley surveyed don’t come to DFT Forum.
Siyad
We’re a Cadence house when it comes to simulation, synthesis and floorplanning. We worked with Cadence to do the layout of our first chip, and they did the test implementation using Encounter Test (indeed, bought from IBM a few years ago). In my opinion, exclusively from the perspective of a customer where our contractor runs the tool, I wouldn’t want to work with it again. It is not as flexible as FastScan and appears to have fewer features.
RTL Compiler however is great in that it has a lot of DFT capabilities built in, no separate license required. It is bad in that it doesn’t have any capability to do hold time analysis, so constraint generation for downstream tools can’t be fully tested. That stinks.
What kind of RTL DFT capabilities are you talking about? Something like Atrenta’s RTL analysis capabilities? For example, does it estimate a fault coverage, and analyze trouble spots?
Nah, not that extensive; more that it can do the equivalent of “compile -scan”, check for controllability problems based upon your declared scan style, etc. But no fault coverage estimation capabilities that I know of.
This is still one of the “big loop” areas, where you find out pretty late in the game that your testability is sub-optimal after someone finally goes to the trouble of REALLY getting the scan fully implemented and patterns generated.
hai i want to insert a different scan cell in my design using synopsys
please can any one help me by sending script file or
detailed explanation how to insert that scan cell thanking u in advance
Please post your question at DFT Forum (www.dftforum.com) There are people that read it that can help you.
Thanks for reading DFT Digest!!
JMF