DFT Digest

… so went the sign-off of a very informative comment by Wern-Yan Koe in a discussion started in the “DFT Experts” group on LinkedIn.  I agree – design-for-test is fun, and challenging.  The technology and methodology advances as fast or faster than in many other electronics design disciplines.  But it pleases me to see someone else put it to words in such a casual way.  Don’t ask why, I can’t explain it.   The same man states his current job description: “Having fun in Design For Test.  A lot to design and a lot to test“.  I think I like this guy… so, now where was I – the reason for this post…

Oh, yes, the LinkedIn discussion.  The discussion was initiated when someone asked about DFT for FIFO and synchronization flops – how to handle scan insertion, should they be scanned, or not.  The submitter received three fairly detailed answers, the first from the aforementioned Wern-Yan Koe, and a couple of others, more or less helpful. Even Mentor and Synopsys personnel chimed in with tool features that may be brought to bear on the problem!

You can view the discussions if you are on LinkedIn, and join the DFT Experts group (believe me, you don’t need to be an expert, they let me in).   But I’m still diverging from the point that I set out to make.

When the DFT Digest and DFT Forum came upon the scene, I don’t think I’d even heard of LinkedIn yet, Facebook was limited to Harvard students, and MySpace was probably the biggest social media outlet.  Now there are several different networking ‘portals’ if you will, and the bust in the economy has been nothing but a boon to these sites.  It’s a great thing for engineers, because up ’til now, communication of tchnology and methodology advancement has been confined to industry trade shows and conferences.

Much of this can now be monitored from your keyboard at lunchtime, or at night, after the kids have gone to bed – and even the least experienced engineer may start or participate in a discussion about how things are done, what tool is best and what company just got acquired.  You don’t have to write an IEEE formatted paper to share your ideas.

LinkedIn participation is pretty impressive – and since the groups funtion has matured, there are many DFT professionals, from the least to the most experienced that have joined DFT Experts; VLSI Design for Test; Semiconductor Product, Test and DFT Engineering; or JTAG & DFT Engineers.  And there have been decent discussions on a variety of topics.

Even newer to the scene, but more focused on our industry, is Xuropa, an online community made up of folks from system design, EDA, semiconductors, IP designers… it’s been pitched as an online trade show – and to that end, as an engineer, you can ask to see product demonstrations, or visit an online booth – and on the flip side, if you’re a vendor, you can present your wares in the form of a lab, booth, or kiosk.

So my point is: The opportunity for communication is out there – it’s everywhere.  Just start typing.