DFT, Really?
I trip upon the following interview in Test & Measurement World – with Joseph Sawicki of Mentor (GM of the Design-to-Silicon Division), and in response to the first question, he says, “DFT is really the fundamental driver of the economics affecting the IC design chain.”
Beautiful! As a DFT guy, I love this. Finally. No one ever talks about DFT in the EDA press or blogosphere (except for me). Even T&M World talks mostly about oscilloscopes, IMHO. But Sawiki hits the nail on the head. If there is a linchpin in the profitability of an electronics enterprise, it’s Test, and DFT drives the efficiency of the test solution.
I like this quote so much, I tweet it. I tweet random stuff like this every once in awhile – nobody really notices. But today, John Blyler of Chip Design Magazine picks up on it, and tweets back, “Joe said that? You sure he didn’t mean DFM? or DFY?“. Chris Edwards (of the Shrinking Violence blog) points out in a blog post almost immediately (before I get back from lunch) that Mr. Sawicki has spent the last ten years driving Mentor’s DFM strategy, and surely folks think I have misquoted him.
In the same blog post, Edwards mentions something that ARM CTO Mike Muller said during his DATE ‘09 keynote – that one class of EDA tools he is most thankful for is DFT/test automation. He was referring to the automation part (stitching scan chains) but also mentioned DFT tools role in yield analysis – DFT tools are the data collection part of DFM, right?
Edwards tweets at myself and Blyler: “Mike Muller (ARM) also very keen on DFT right now – it’s all to do with the yield analysis and management features“. Blyler, still unbelieving, tweets back at Edwards: “‘ARM keen on DFT.’ Can you point me to a recent article? And why call it DFT? Does it affect test more than manufacturing?” I suppose he is talking about the data collection.
But the interview with Sawicki really only touches on DFM briefly – the main topic is Mentor’s DFT tools – he talks about scan, boundary scan, memory test and logic BIST. And the follow-up to his first sentence that I tweeted – explains his statement. Here’s the whole thing:
DFT is really the fundamental driver of the economics affecting the IC design chain. It’s the primary method of eliminating defective parts. If you do a poor job of test planning or if you introduce ineffective tests, you risk damaging product quality and your company’s reputation. Test costs also have a direct impact on the cost of goods sold, which is why it’s essential to prevent inefficiencies in manufacturing tests that cause false rejections and reduce yield. There’s a major trend toward leveraging test and diagnostic information over a product’s life cycle to improve yield and company profitability.
There you have it. Quality and efficiency of test go straight to a company’s bottom line, and its reputation. DFT has always been about manufacturability – since way before the term Design for Manufacturability was coined. And its a key piece of your new DFM flow that nobody ever talks about…
I don’t get no respect! No respect at all!
- Rodney Dangerfield, surely one of the first DFT engineers
Stumble It!
John,
Just to be on the record, I’ve been a fan of DFT as a cost-savings metric for a very long time. It’s the most fascinating part of EDA but should be part of Semicon, not DAC.
I have you on record Lou – and it may be better served at Semicon – it could then be closer to its ATE roots.
However, DFT has always had a dualistic nature – is it test? is it design? (”you got your peanut butter in my chocolate! You got you chocolate in my peanut butter!”
Today – and I mean literally today, I’m a bit intrigued about how a couple of interviews and blog posts could convey somehow that “DFT is the new DFM”[?] – it’s not that at all. DFT provides a window with a view of the success (or lack thereof) of a DFM process. At least that’s how I understand DFT w.r.t. DFM. But DFT stands on its own as a catalyst for better profitability.
Hi John. I was using editorial license (and trying to stay with Twitter’s 140 character constraint) when I wrote that “DFT is the new DFM.” But they are very different processes and life cycle phases, as you note and most engineers understand. The only commonality that they share is that they are DFX requirements, i.e., both must be considered in the design phase of the system/product development. Nite.
Hi John – thanks for commenting – I get it now. It caught my eye, because it didn’t seem to reflect what Sawiki and Rasjki were saying – but you have a talent for writing headlines that draw folks in!
Twitter is great practice for that.
Thanks for reading and commenting,
JMF
Glad to see the pick up on this. There is far too much chirping going on in the blogsphere these days about the “death of EDA” and far to little on the value being produced by the industry. We’re in the midst of a very challenging semi downturn that makes it easy to become morose, but if we focus on value, effeciency and making the customer successful we’ll manage through this.
A side note: though my family often has discussions on the many ways our name could have been spelled (especially as we search in vain for my Grandfather’s birth certificate), I would tend to agree with the immigration service who settled on SawiCki about a hundred years ago. According to about.com (http://genealogy.about.com/cs/surname/a/polish_surnames.htm ) it is one of 50 common Polish surnames.
Joe
Hi Joe:
My apologies for the misspelling of your name – I updated the post (which also had a broken link to the interview – really, I guess I need more sleep!!)
I agree, EDA’s not dying, just changing, as it always will. My beef, as a DFT engineer, is that so little attention is paid in the press, blogs and elsewhere to DFT – that’s it’s not very well understood, and people will try to morph it into something else, or relegate it as a simple enabler for a “really important technology”, such as DFM. DFM is important, no doubt, but DFT, as I say, stands on its own for the reasons you so clearly articulated.
BTW, what do you think of Lou Covey’s suggestion in this comment thread about showing DFT tools at Semicon rather than DAC? After a quick look at the DAC program, there’s nothing to draw a DFT guy to the show at all, this year – Ron Press’ reduced test routing talk seems like the one lonely DFT related event…
Thanks for commenting – again sorry about the misspelling
JMF
If you look at the research done in DFT and DFM since the 1970s, you will see that many researchers were involved in both DFM and DFT. A key reason for this is that few digital designers were interested in DFM (a group from Motorola once told me that six sigma would solve all of their yield problems), but test engineers were interested in what Intel engineers eventually called defect-based test. Similarly, these same researchers have been advocating since the 1970s that test was essential to diagnosing yield problems. For years the marketing managers at one big EDA company would respond “show me the money” when I would advocate their investing more in diagnosis. That same company now has probably the most FTEs working on diagnosis and test-based yield analysis. As the quotes above indicate, the money has finally arrived.
Hi Hank:
Welcome to DFT Digest! Funny, I started out as a test engineer in the early 80’s and remember well the data collection, number crunching and plotting we had to do in order to prove that everything fell within 6-sigma. I don’t miss that.
Interesting historical perspective – I guess DFT development went down the path of least resistance. But with higher frequencies and smaller geometry, it needed to change direction. The recent interest in adaptive test seems to be an indicator of that.
I find it interesting that between the two largest DFT vendors, one is concentrating on the defects (although, different kinds of defects), and the other is really pressing the diagnosis and yield enhancement route.
Thanks for reading and commenting. I look forward to hearing more from you!
Cheers,
JMF
John,
This post and comments on the thread are really interesting. As a DFT guy, I find it music to ears
I understand that DFT is seen as a key driver to reduce or at least manage cost. I think DFM goes much beyond that. One of my friends had a title as ‘DFX engineer’ in one a big semiconductor company and he worked on anything that had to do with test, manufacturability or cost reduction. Other companies who did not see it that way have tried to “compartmentalize” the issues. Isn’t that so?
Cheers,
Sagar
Hi Sagar:
‘DFX Engineer’ – I like that title. It definitely covers a lot of ground, and if you’re at a big semi company, I guess you might be able to have an influence in all that DFM covers. And one would have to be just as versed in design concepts as process issues. Your friend must be very versatile. So in some ways, compartmentalizing is just necessary, because it’s hard to find someone like that. But on the other hand, maybe having a *group* like that would be a great thing, as long, as I say, you have influence over all those domains.
Thanks for commenting!
JMF