DFT Digest

From time to time, I go over to EDABoard, a fairly all-encompassing electronic design bulletin board site operated from Europe, and check out the ASIC design forum. It seems that design-for-test is a fairly popular topic over there. There’s plenty of people not even sure where to start with DFT. I try to lend a hand when I can.

The most popular question is “What is DFT?” or “Where do I start?” - “Why add test logic?”. The typical responses from the crowd are of the short form: “DFT = Design-for-Test”, or “check out this book…”, which, to me, are valid responses. A forum is a hard place to explain a whole facet of ASIC design. Believe me, I’d like to write a lot more in this blog, but it’s time consuming, and well… never mind.

But what I find more interesting are the more focused inquiries, where the true misunderstandings are in design-for-test methodology. Looking back over a few pages of topics relating to DFT, I can come up with a few common threads:

• DFT Compiler related questions - Anywhere from trying to figure out why scan chains were not inserted to outright asking for DC scripts, accomplishing the work of scan replacement and insertion is a pretty hot topic.
• Multi-clock domain scan implementations - Many are curious what to do with these, how and when to use lockup-latches, and whether to use one or multiple clocks for the scan chains. Makes for interesting conversation.
• BIST related questions: How to design it, build a bypass, figure out the low fault coverage around BIST implementations. However, people seem to go about it a bit backwards - most don’t seem to know there are tools dedicated to generating BIST for embedded memory.
• Handling of exceptional cases around the scan design, such as bi-directional pins as scan pins, tristate buses
• ATPG verification and simulation mismatches - big topic. What happens when the simulations, or the ATE vectors fail? What’s the likely cause? What format to write? Then what?

Really, a good variety of questions. I’m actually surprised at the frequency of DFT questions popping up on the board - heck, in the larger EDA media, it gets very little mention.

One thing for sure, it’s a great place to pick up a few good interview questions…