DFT Digest

Tonight there will be all manner of kids, big and small, traipsing through your neighborhood, masquerading as one thing or another. Be kind, or be tricked… Last week, at ITC, I felt a little like a trick-or-treater, walking around dressed up like a real DFT engineer.

Well, yes, I am a DFT engineer, and I have been hanging around the semiconductor test industry for many years, but ITC always makes me feel this way. I’ve actually only been to two ITC weeks. This was my first in 9-10 years. I went to a VLSI Test Symposium once also. And I always feel like a bystander among some very hard-working engineers who are consistently striving to keep the electronic test industry where it should be with respect to other electronics disciplines.

In general, for me, it was a successful trip. I re-connected with colleagues from “past lives”, and met for the first time some others who opened my eyes to new directions for this blog. Everyone I approached with the idea seemed to be supportive and positive. Now if only I can start registering some of these people. However, I will always grant partial immunity for some of those who are busy being one of those hard-working folks mentioned above. Partial.

I’d like to report on everything I saw and heard that migh be of interest, and I probably will, but it will inevitably span several posts. Where to start? Find out beyond the link…

ITC has certainly changed in the years since my last visit. During my last visit, I was able to walk up to the newest, fastest, sleekest ATE on the market, and see it test the most challenging circuits of the day. At the time, it was probably a Teradyne Catalyst, or maybe an early version of the LTX Fusion (although, that might have come along later).

The largest booths by a long stretch are now EDA companies. The “big iron” has gone the way of the dinosaur, as far as ITC is concerned. Agilent and Credence both had booths, but no hardware, and neither LTX nor Teradyne were to be seen. I guess when a test head and manipulator weigh more than a Hummer, you’ve got to pick and choose your destinations.

As a DFT engineer, I was most interested in the EDA companies anyway. Being in an evaluation cycle myself, I was particularly keen on listening to what direction each vendor (read Cadence, Mentor, Synopsys) was going. In conjunction with the general push in the industry towards DFM, the two main themes in DFT for the big three seem to be small delay defect coverage via “faster-than-at-speed test”, and power-aware DFT.

All the tools seem to be incorporating, or have already incorporated some ability to read design timing information and use it to pick more timing critical paths to satisfy the coverage of a given fault condition, rather than picking the easiest. This, combined with at-speed scan, tends to catch “small delay defects”, more prevalent in smaller geometries.

Power-aware ATPG is also a hot area. There are multiple methods for powere-aware test; some involve changing the nature of the fill data used after care-bits have been controlled and observed. Both Cadence and Synopsys offer this capability. Other methods involve partitioning the design during test to prevent the whole chip from being toggled at once. Another interesting offering from a collaboration between Mentor and LogicVision uses a ramping of the at-speed clocks before and after launch and capture to avoid instantaneous voltage drops in the power grid during this time.

Well, that’s all for now, but there’s much more to come, on subjects such as JTAG, DFM, and SerDes Test.

It’s all good…