DFT Digest

Design for Manufacturing (DFM) delves into a few different disciplines within the chip design arena. It involves not only the designers, but the EDA vendors and manufacturers. The heart of it seems to be the physical design aspect. Maybe in one sentence, DFM seeks to maximize manufacturing yield by following certain physical design rules. I liked the definition given by Andrew Kahng of Blaze DFM in a recent interview with Peggy Aycinena at EDA Confidential:

1) It must communicate the intentions of the designer to the manufacturing flow.

2) Bring manufacturing awareness up into the design flow.

3) Accomplish the first two precepts transparently with respect to today’s flow and manufacturing interface.

So where does DFT fit into ths? Well, first I would say that DFT fits into the measurement/analysis phase of a flow that implements DFM. Because the only measure of DFM is yield at the ATE, and the analysis of the yield fits nicely into ATPG tool diagnosis features. With tools being introduced today, ATPG fail data can be brought back into a physically aware design database and used to pinpoint failure sites in the layout. Cool.
But that’s after the fact. Can DFT tools be leveraged to contribute to the success of a design before it’s taped-out? It seems like they should. If ATPG tools can be made to detect likely bridging faults, maybe a combination of going through the normal DRCs and iteratively trying to minimize the number of patterns genarated by probable bridging faults with a physically aware ATPG tool would help to dial up the yield pre-tapeout?

Anyway, it sounds like an interesting conversation…