DFT Digest

I’m having the hardest time ever keeping up on the blog this month. Call it an extended holiday hangover, crunch time at work, short spates of illness, whatever. I hope February sparks up here for me.

Last month I started writing about testability or DFT planning. Of course, I took the easiest route first. Full scan and memory BIST! Logic BIST! Easy for all digital chips. Didn’t mention JTAG, but I should have, since that’s another area where automated test insertion has worked for many years.

So, yes, we went over the low hanging fruit of the bulk digital logic. Those measures cover the mass of (usually) standard cell, scan-inserted logic. But in every sea of digital circuitry, there are spots where scan insertion is either not possible or imposes an unreasonable timing or area penalty. What methods are available to test this logic?

More after the click…

One alternative to structural test, of course, is to functionally test the circuit. In this case, access is the key. If the area is fully accessible, this can be done. If not, some sort of access must be designed in. One of the more popular ways to do this is to share input and output functionality at the ‘primary I/O’ level. In a test mode (enabled either by some primary input configuration or by writing to a register), device input pins can directly stimulate the embedded non-scan circuit, and the embedded circuit’s outputs can be observed at shared outputs. At this point, vectors to exercise the logic can be written, simulated, and translated to ATE format.

All that is nice if the pins are available to do the job. However, this may not be the case. Sometimes it’s not possible to bring out the pins. There are other alternatives in this situation, but how you go about it depends upon the circuit under test (CUT). If the CUT is a small memory, for example, not deemed big enough to BIST, you could choose to use the surrounding scan chains to test it.

If the CUT is a small section of embedded non-scan logic, depending upon its structure, you may be able to use the ATPG tool to test it. If it’s very small, and sequentially shallow (4-5 stages, max – I did say very small), you may be able to run your ATPG in sequential mode, and target just that section of logic, and get away with it. This will probably not be the case most of the time, but it’s an alternative, nonetheless.

If the embedded circuit is larger, or is an embedded memory (in which case the ATPG cannot create patterns for it at all), you might be able to still use your scan chain, but in this case to provide functional stimulus and collect the response, one vector per scan load. Many people use this methodology for small, embedded memories that are too small to consider a BIST implementation. Basically, the ATPG tool does the hard work of taking the stimulus and expected response that you provide, and figuring out how to deliver and collect it using the existing scan structures.

Mentor provides this capability with a Fastscan extension called MacroTest. Synopsys calls their offering PatternMap, a feature of TetraMax

When you think about providing stimulus to an embedded circuit using a scan chain, you might start your sentence with, “What the … ?. Well, yeah, I can see how that would work, and it’s pretty clever, but – wouldn’t it take…forever?�

Personally, it reminds me of a quote I’ve seen, attributed to T.W. Williams (a Synopsys Fellow): “Using JTAG for test data is like sucking the ocean dry with a straw!� That’s pretty much how I feel about this method of testing an embedded circuit. It’s slow, and can consume an enormous amount of available vector memory, if the circuit’s sufficiently large, and you want to do a decent job of testing it. Notice the emphasis on decent, as in only decent. Remember how good functional vectors generally are.

Until next time…