DFT Digest

It seemed like a long day – but it was actually shorter than most normal work days. But – some days at work, the most advanced DFT concept I utter is “no, the clocks need to be controlled from the primary I/O during scan shift…“.  At the International Test Conference, the discourse runs a bit loftier.  You gotta work harder to pay attention…

First off, I do believe I made a reference in my last post to the Synopsys SIG event Monday night – I believe I said “Good food, interesting presentations”.  It’s true, I admit, I liked the food.  Don’t hold it against me.  But, of course, that’s not what we all came for – the reason companies throw parties like this is to put their best foot forward, and show the customers what they can do with their tools – using customer testimoninals.  The focus of the presentations honed in on the Small Defect Delay (SDD) transition fault ATPG capability of TetraMAX.  TI Fellow Ken Butler introduced three speakers, all presenting different aspects of TetraMAX, focusing both on its applications to certain test problems and its tight integration with other tools in the Synopsysy flow.

Mentor Graphics held their technical event today at lunch.  In contrast to the focus on ATPG at the Synopsys event, Mentor put forward their strength in the volume diagnostics and yield analysis area.  A customer(?) testimonial was given by Stefan Eichenberger of NXP – detailing the power of volume diganostics.  I use a question mark after “customer”, because, NXP and Mentor are sharing DFT technology – so who knows who’s working for  who?  Mentor marketer Brady Benware drove the point home with more strategies for diagnosis and yield analysis. Sorry Mentor – I didn’t like your food as much…

The plenary session was kicked off with the keynote speech given by Mike Lydon of Cisco, who actually has 9 words in his title (seriously), is in charge of supply chain management at Cisco.  His primary message to the crowd was a call to find ways to be able to share product information, so called “key attributes” between supplier and customer, to cut down costly failure analysis loops in the supply chain.

As just mentioned, the Mentor technology event spanned lunch, and following that, was the Microprocessor Test session, with three interesting presentations, all addressing multi-core test strategies.  Mostly good stuff – all presenters went a little long and bravely endured stares from the session chair, Doug Josephson of Intel.  No seriously, I wouldn’t @#$% with him – just ask the poor sap that tried to short cut a walk to the microphone and ask his question from his chair in the front row…

I intended to attend session 6 on delay test, but ended up talking with folks on the exhibition floor – I talked with Jin Johnson of SiliconAid, and sat down for a demonstration of SiliconAid’s JTAG validation software products, and took a picture of myself punching George Bush, to print on a coffeee mug – I still don’t have my mug.  In fact, I don’t have my mug from two years ago…

I haven’t yet mentioned the exhibit floorplan, but it’s changed since I was last there two years ago… at least as far as where the big EDA companies were placed – as if it means anything… really.  But it seemed, in contrast to two years ago, that all the big EDA vendors were all shoved together on one side of the floor, and that’s where all the traffic was – the smaller test instrumentation type displays were all off to the other side.  Much less activity.  The Cadence booth – significantly smaller than the last time I was there, and tucked in back of the two biggest booths, Synopsys and Mentor.  Interesting, that’s all…