DFT Digest

Happy Sunday!  Test week is over, participants are back to their normal lives, perhaps off to another conference.  Last time I blogged, it was Monday, after the first panel and 40th year reception.  I’m going to try to blog a few notes throughout this week, including some from conversations with folks from Cadence, Mentor and Synopsys.

Tuesday was the first day of the conference proper, so participants gathered in a large ball room for the keynote and invited address – I, the lone twitterer of ITC2009 (@dftdigest, hashtag #ITC2009), tapped out a few notes during the speeches.

Antun Domic of Synopsys delivered the keynote, in which he talked about the various complications of non-design-aware test implementations, and called for a “DFT flow”  that is aware of every part of the design process.  He considers this “DFT flow” (as opposed to “DFT tools”)  is necessary for the successful implementation future IC designs, and notes that the industry is not quite up to the task yet.

Domic asserted that it is necessary for exploration and investment to develop these flows, and  compared these activities to that of Christopher Columbus (explorer) and Queen Isabel of Spain (investor), and displayed the following quote, which if I remember correctly, he attributed to Columbus:

“One does not discover new lands without consenting to lose sight of the shore for a very long time.”

I like the quote, but as I looked it up on the web (to make sure I quoted it correctly), I noticed that it’s actually attributed to Andre’ Gide, a 20th century Nobel winning author.  Either way, I got the point – and as I said, I like the quote.  One could apply it to many things.

[update: Robert Ruiz of Synopsys was kind enough to send me the slide in question, pictured below. As you can see, down there at the bottom, the quote is correctly attributed - no wonder I didn't see it - I was sitting in the back row!]

Domic was followed by Shekhar Borkar from Intel, who laid out a very technical analysis of the current state of chip design, and how it might scale (or not) into the future.  Ron Wilson, covering ITC for EDN and Test & Measurement, wrote an excellent summary of Borkar’s address.

[BTW, Wilson also blogged the Stanford CRC panel, as I did in my last blog post]

After the plenary, exhibits opened, and technical sessions started.  A quick look around the floor showed the continuous contraction that this show has been experiencing over the years.  Years ago, the ATE companies left – the only ones left this year were Verigy (with a tiny booth) and Roos.  The biggest surprise to me was the scaled down Synopsys booth.  Last year, Cadence was off on the sidelines, with Mentor and Synopsys at the center.  This year, Mentor anchored the entire floor, with the rest of the field cramming into cubicle sized booths.

One humorous note: after the flack at DAC amongst the journo/bloggers about the XJTAG booth babes (see this, this, and this), I didn’t expect to see them at ITC.  Not that it bothers me.   Siliconaid staffs its booth similarly every year at ITC, and I’ve never heard any complaints, just amused chuckles…

Two panels on Tuesday afternoon, Can EDA Help Solve Analog Test and DFT Challenges? and Testing of 3-D Chips: Is There Anything New Under the Sun? both seemed worth attending, but I opted for the first – I’ll blog that later. Can’t wait? Ron Wilson wrote it up here…