DFT Digest

Another October has come and gone, and those determined folks who do their best to ensure that only good electronic components and systems are shipped to customers will be making their way back to the home base.  That’s it for the 2008 version of the International Test Conference.  So what were the big ‘take-aways’ of this years conference?

The conference was capped by invited addresses (Lydon, Rearick) that stressed the importance of propagating the value of DFT and test into all parts of the supply chain, so the benefits may be reaped both upstream and downstream.  This notion, I think, is important to the future of test and design-for-test.  More than being the other side of the wall, the tools that facilitate test will also facilitate quality - not only by making better tests easier to implement, but providing the data and metrics needed to drive quality in the right direction.

Indeed, for some, the most interesting information shared at ITC was that concerning the information gathered during test used to diagnose failures and process variability.  Ken Butler, TI Fellow, pointed out a couple of papers that caught his eye: paper 1.3: Efficiently Performing Yield Enhancements by Identifying Physical Root Cause from Test Fail Data, paper 10.2: Statistical Yield Modeling for Subwavelength Lithography, and paper 14.3: Unraveling Process Variability for Process/Product Improvement.  For Butler, these types of papers are a natural for ITC, and he hopes to see ITC content trend in this direction.

The other big story, and maybe the most controversial one, was power.  The conference opened with a panel on test-mode power, and it remained a hot topic all week long, to the surprise of some people.  Matthias Kamm of Cisco commented, “I was surprised there were several papers (Freescale) and references (Sun, others) to the VDD droop ’slowdown’ issue during at-speed test.”  Ken Butler was equally impressed. “I was a little surprised at how much work there is going on in the power area. Power is definitely a concern, but there clearly seems to be a lot of focus on that topic – More than I expected to see.”

All the EDA vendors in attendance put forward their power-aware solutions.  Several papers, a panel, and a Hot-Topic Background Session were devoted to the subject - was all the attention warranted?  Depends upon who you talk to, of course; regardless, everyone seemed to be talking about it.  Discussion centered on minimizing test-mode power, rather than how to test power-reducing design features, and in particular, focused on scan-mode power consumption.

Normally, EDA/test vendors announce new products around ITC time - this year there seemed to be less in the way of new products, and more in the way of new partnerships: Teseda announced cooperative agreements with both Teradyne and Mentor, tying together Teradyne’s mainstream SoC ATE platforms wih Teseda’s diagnostic software and Mentor’s yield learning software.  This extends a recent trend in the industry, started by Verigy’s acquisition of Inovys last December - a sort of vertical integration of DFT, Test and DFM that could use some further exploration (a good topic for blog me to blog in the near future).

Other examples of announced partnerships include Asset Intertech joining Synopsys’s In-Sync program, Teradyne and JTAG Technologies cooperating on board test, and Goepel and SPEA extending JTAG functionality of SPEA probers.   With as much activity (at least in the form of announcements and press releases) that occurs in the PCB test arena, seemingly every month, one would think ITC would contain a bigger chunk of that type of content.  However, as in most years before, there was very little (I count 2 sessions and a lecture) on board-level DFT/test.

Looking forward: ITC 2009 will be held in Austin, TX in the first week of November, 2009.  It might be nice to visit Austin again.

BTW: Looking for some pictures of ITC?  Someone from EDA Cafe took some…