DFT Digest

It’s not really the first day of the International Test Conference (tutorials started yesterday, and the actual conference kicks off tomorrow), but just to get *warmed up*, there was a special panel held to explore the *hot topic* of power-aware test: Power-aware DFT - Do we really need it?, moderated by TI Fellow Ken Butler, who was joined on stage by 5 panelists: Jeff Rearick of AMD, Bahram Pouya of Freescale, Srinivas Patil of Intel, Prabhu Krishnamurthy of LSI, and Bill Huott of IBM.

Dr. Butler started off by answering the question with a question (so admirably stated by a former president): “It depends upon what your definition of who we is…” At this point he broke out the hats (literally, baseball caps) of all the stakeholders of power-aware DFT: microprocessor engineer, DFT engineer, EDA vendor, etc., and as a nod to the political season, one for Obama, McCain, and Palin.  Each speaker during the evening was passed a hat representing their stake.  Savita Banerjee of ST later commented that she couldn’t afford the Palin hat

This was followed by ‘lightning talks’ by all 5 panelists, stating their positions on the matter at hand.  Jeff Rearick felt it obvious that these *burning issues* (his term, very punny) need to be addressed, and suggested that most of what we were talking about were DFT for high power, not for low power.  This theme was re-stated, although differently throughout the night, that there are two issues: DFT for high power consumption/dissipation (manging test-mode power), and DFT for testing power reduction features in low-power devices.

Bahram Pouya of Freescale called power-aware DFT a “journey, not a destination“, something one usually hears when disapointed with results.  He would be the first, but not the only person to mention that test-data collection is an important piece in solving test-power issues, and that this piece is not where it should be.

Srinivas Patil of Intel offered immediate disclaimer that he was a stnad-in, and just doing a brain dump, and commented that this issue is not new, been researched increasingly over the last decade.  He actually had a slide that seemed to show the results of an experiment using fast scan shift clocks as a preamble to launch/capture clocks to even out the peak power experienced during that time in at-speed vectors.

Prabhu Krishnamurthy of LSI contended that test-mode power is not a yield limiter today, and offered up a survey of problems to be solved in testing low-power design features (power islands, partitioning, isolation, shut-down/wakeup modes and multiple bond-outs).

Bill Huott of IBM asked by way of analogy “Power-aware DFT - Do we really need it? Tachometers in cars, do we really need them?” I guess the answer is only if you’re looking… but he’s obviously looked, because he presented some very fancy PowerPoint slides showing the power map of a large chip drooping all over the place, and very extremely so (400 mv in a 1.2v power plane is significant, I think we can agree).

The audience perked up and asked a few questions, well most of them were questions. Yours truly, having noticed that someone (I don’t remember who) mentioned memory test as part of the test-mode power issue, asked why it was never mentioned again. The answer came back, if I can paraphrase: “All those problems are solved, like last century!” oops…

Later: SIG event… good food, interesting presentations…