DFT Digest

How do you repair a memory?  You don’t, once brain cells are dead, they’re dead – right?   No problem, we all use only about 10% of our brains, so there’s plenty left to work with – 90% redundancy!

OK, well that 10% story is a huge myth, but having extrabrain cells to work with is a decent analogy for how we attempt to improve yields during the test of embedded memories.

Memory BIST implementation has been standard practice in the industry for many years. But for the past few years, those that keep track of the trends have pointed out that an increasing percentage of silicon area in our chip-level products is taken up by embedded memory. So BIST is good, right? Yes, of course, but multiply the increasing area by the fact that memory structures are inherently more dense than standard logic, and you have a potential yield problem on your hands. Any defect that might ’slip between the cracks’ in a standard logic area, most certainly won’t in a memory array. For this reason, memory diagnosis and repair algorithms were developed – a.k.a Built-In Self-Repair or BISR.

Memory repair is not really ‘repair’. It’s redundancy and re-direction. Electronic sleight-of-hand, if you will. For each array being ‘repaired’ there are a certain amount of extra rows and/or columns set aside so that if bad bits are found, there are extras that can be used in their place. Every time a bad bit is accessed during normal operation, the addressing logic actually accesses one of the spares. This, for efficiency reasons, is done on a row or column basis. If one bad bit is found, the whole row or column is replaced.

Now obviously, you determine where the bad bits are by testing the memory during the manufacturing test process. Once the bad cells are found, then on-chip algorithms are enabled to determine the best use of the extra rows and/or columns to replace them (These algorithms are called BIRA, for Built-In Redundancy Analysis, and are very different than those implemented in software on memory ATE).

If all the bad cells in a faulty memory cannot be covered by a combination of spare rows and columns, the memory is considered ‘unrepairable’. If the memory is ‘repairable’, then the extra rows/columns will be used in an optimal way each time the device is powered up. How the extras are used must be coded and stored somehow.

The most common way for this to be done for SoCs (memory vendors have different, more optimized methods, I assume) is the use of the electrical fuse array (non-volatile storage).  When the repair signature for the  combined set of memories has been determined, it is shifted (most likely in compressed form) into the fuse array, and the signature is then burned into the array (a device pin capable of delivering high current to the fuses does the ‘burning’).

Once this signature is permanently in the fuse array, then whenever the device is powered up, the fuse values are decompressed and shifted into the repair circuitry of each memory to be repaired.  This whole process of testing, analysis and repair is called ‘hard repair’.  In addition to hard repair (or in place of it), an extra test/repair operation may be done after power up, called ’soft repair’.  The repair signature from soft repair is not saved, so it must be repeated each time the device is powered up.  Since this is time consuming, and is only done at power up (before the chip has heated up), there is concern that using only soft repair is not very reliable.

That’s the nutshell – have any questions about memory test annd/or repair?  Comment below, or post your questions to DFT Forum.  You can also read up on it yourself in this  book, or google memory BIST (the first link in this search is a very comprehensive presentation by Cheng-Wen Wu, same person that wrote the memory test chapter in the book).

Cheers,