DFT Digest

Remember in my last post, where I told you how weird it was to suddenly be seeing all these references to 3D ID design technology? Well it didn’t stop. Literally, the day I posted that entry, I got the new issue of IEEE Design & Test – a special issue on, you guessed it: 3D IC Design and Test.

The same day, I was cleaning my desk, and found a couple of papers that I had printed out a couple of months ago and forgot about, from DATE ‘09. One was entitled Test Architecture and Optimization for Three-Dimensional SoC’s.

Just one more: Scott Hack commented on my last post, directing me to an article written by Al Crouch at SoCCentral [hey Al, how about an article for DFT Digest?], entitled Test Standards Emerge to Improve 3D-Chip Yield. Good article, I enjoy Al’s writing style – he makes it very easy to grasp the concepts he’s trying to convey.  Basically, he runs down the applicability of the new IEEE 1149.7 and P1687 (IJTAG) to 3D-IC testability.

But back to that D&T special issue: I’ve probably said this before, but I always look forward to getting this magazine (it’s a bi-monthly occurrence).  It’s usually got something that gets my interest, even if it might be steeped in a crapload of math.  I can usually get the gist of the articles.

This issue has several interesting articles, and not just on 3D technology.  There is also a special section that highlights some of the best stuff from ITC 2008: three articles, including one on mixed-signal production test methods, by Gordon Roberts, and one on Staistics in Semiconductor Test, by W. Robert Daasch, of Portland State.

The 3D section of this D&T issue contains four articles, including one that directly addresses the Test Challenges for 3D Integrated Circuits (by Hsien-Hsin S. Lee and Krishnendu Chakrabarty).  Test is one of two main challenges that crop up when designing in 3D – the other is power (thermal issues).   I think I’d like to summarize that article, and the others on 3D test that I’ve mentioned here in a future post.  There’s a lot to think about.  By the way, you can download and read a pdf of the Guest Editor’s Introduction to the special issue here.

It’s been pointed out here and in other places that 3D technology is one of the hottest topics at ITC next month.  A quick look at the advance program reveals only two items that specifically mention 3D: A panel discussion (Testing of 3D Chips: Is there anything new under the sun?), and an embedded tutorial (Testing 3D Chips containing Through-Silicon Vias),  However, as both Bill Eklow and Erik Volkerink pointed  out in interviews with DFT Digest and Test & Measurement World, there are some board-level test items and emerging standards sessions that will most assuredly contain 3D content (for example, Embedded Tutorial 3: New Boundary-scan-based Standards).

See you at ITC!