Power Hungry DFT??
I’ve run across a couple of items in my reading lately about concerns with test-mode power. Not that it’s a new issue, but sometimes when you’re looking for something else, a subject will jump out you a couple of times, causing you to take notice.
Much has been studied and written about test-mode power consumption in the past few years, especially as “at-speed” scan methods have matured and become mainstream. Several different approaches have been considered for dealing with it. DFT tool vendors offer “power-aware” products to mitigate the effects.
The idea is that during ATPG, for example, or logic BIST, most if not all the flops in the device are toggling at once, perhaps for an extended period of time. The massive power draw due to above normal switching activity may cause damage to the device, resulting in reliability failures, and/or lower than normal yield at time zero, especially during at-speed test. Instantaneous switching power can cause voltage drop in the power grid, slowing down the logic and causing false negative results.
I think a good discussion of the different aspects of this issue and methods for mitigation is in order - it also ties into our on-and-off discussion of DFM issues.
Stumble It!
[...] So is Mr. Jackson creating a new design discipline? No, maybe just a new term. Maybe it’ll catch on. Regardless, it doesn’t take away from the points he’s trying to make in the article. Some of them I’ve touch on in earlier posts, such as being aware of the effects of all of the flops on your device being toggled at once during ATPG - it may be more activity than ever seen in functional mode. Test compression may exacerbate the problem, and since test compression is designed in ahead of time, ahead of time is when you need to think about it. [...]