Protocol-Aware ATE – Next Big Thing?
“In my opinion, this is just the biggest thing to hit ATE ever. Anyone else feel the same?”
My curiosity piqued, I started googling, and found that there were 3-4 papers, and a panel discussion on the topic at ITC 2007. The idea was apparently broached originally by Andrew Evans, a test engineer at Broadcom, in a call to the ATE industry to start thinking about producing testers to operate at a higher level of abstraction, to pull test engineers out of the low-level bit/edge pushing that they seemed to have been trapped in since the beginning of time. Been there, done that, hate it, I agree!
Anyway, to try and push this idea into a small enough nutshell to fit in a blog post, protocol-aware testers would be able to 1) operate on higher level commands for protocol-based interfaces such as JTAG, I2C, or SPI in the simpler cases, and PCIe or DDR in the more challenging cases, and 2) be able to handshake with the DUT. Imagine that.
Sounds like a dream – but not all believe it can bring reduced development time or improved quality. As Steve Sunter of LogicVision points out, the lower level protocols are already sufficiently automated (and the time-to-market advantage would be minimal), and for DSM designs, the incremental quality (over structural test) gained from implementing the higher-level protocols would be dubious at best.
Al Crouch of Asset Intertech chimed in on the LinkedIn discussion, pointing out that higher-level protocols are more complicated, from an ATE point of view, than meets the eye:
Protocol Aware testing has a lot more involved than is first thought. There is the obvious “functional test” aspect (delivinging functional vectors using the protocol — such as PCIe) where the ATE must respond to the protocol (e.g. the chip may request a re-transmit and the ATE must respond correctly; the ATE must request a re-transmit — not just take the first erroneous value returned as a fail).
It’s unclear at this time, to me (although I’ve done precious little research to date), what protocols and capabilities will be available in the first protocol-aware ATE resources on the market., but I’ll go down as agreeing with Steve Sunter in concluding, for now, that protocol-aware ATE can be a complement to structural DFT. It’s about time the ATE industry transcended the one’s and zeros’s of the physical DUT interface.
Anybody want to chime in on this some more? Either comment on this post, or contribute to the discussion on LinkedIn…
Stumble It!
Seems like the “link” to LinkedIn doesn’t work if you don’t belong to the right LinkedIn Group. And LinkedIn doesn’t show the name of their group to which you must belong!
Thanks for the heads up, John – I’ll have to figure out how to do this right!
The group name is:
Semiconductor Product, Test and DFT Engineering
But I guess if you’re not part of that group you can’t link straight into it. In fact, I’m not sure you can see the discussion at all if you’re not in the group.
Sorry about that folks…
JMF
One comment about Austin’s quote, “Protocol-Aware is the biggest thing to hit ATE ever.” I’d say the biggest thing was the switch to structural test. Just ask “Schlumberger ATE” with regard to Intel’s switch from functional to structural. This has also driven down the cost of ATE. It hasn’t devastated the ATE industry, but certainly has made a huge impact… For DFT verification and characterization we all but replaced our $5 million big iron ATE with a system at 1/10th the cost. Teseda has a small desktop system for a fraction of that…
Back to PA: Boy, wouldn’t it be great if someone from an ATE company leaked preliminary info on their PA card? I’ll guess PCI Express 2.5G as an intro instrument. Someone needs to start http://www.ateleaks.com
Yeah, probably the better statement would be “the biggest thing in ATE in the last 15-20 years”? As far as http://www.ateleaks.com goes – the domain name is open, are you volunteering?
I’ll say, “the past 3 years.” Could be interesting for folks who still run some functional “top off” tests to ensure high quality, or for DV/Bring-up of new silicon.
As Steve pointed out, Jtag and other lower speed protocols have been automated for some time.
The subject of PA testing is getting more interesting when considering the more ‘analogue’ aspects of circuits at high frequency. Either a BIST approach is adopted with loop-back for serDes links such as MIPI, DigRF, or the surface area is saved by putting the test in the tester. However, it would appear the tester instruments would have to be very flexble to manage a given protocol and any slight deviations that were either non-conformant with the protocol spec, or simply to avoid a dedicated instrument per protocol. Could all this flexibility be achieved using FPGA’s in the tester hardware ? Any ideas ?
The other issue is density. Many ATE pin electronics are dense liquid cooled electronics and achieve 2048 pins in a reasonable testhead area. FPGA’s are pigs in terms of real estate. I think we’ll be looking at relatively low density instruments.
Yes, but most testers also have area set out for special resources, such as high speed clock cards, Gbps SerDes cards, etc… and these don’t necessarily eat into the regular digital pin density – or am I wrong about that?
I, of course, favor the DFT approach of BISTing these circuits, to keep the tester costs lower.
JMF
It depends on the platform – for many a slot is a slot. You can fill it with an AWG, a low density high speed card, or a high density low speed card. There’s an opportunity cost in terms of top end pin count or capability once you fill it.
The other advantage of a DFT approach is the leverage the xBIST can give you downstream. We run some bist on the ATE, during board manufacturing, and even in the field during POST.
Doesn’t protocol aware testing comes along with asynchronous testing?
Shouldn’t we always consider how many protocols must be executed in parallel in real time? For an approach to test only one protocol at a time you just need a match functionality to record all data and analyse them.
More effort you have to spend if you need in a communication parts reused like random numbers in RFID testing. Here a good architecture is mandatory. At Konrad we look to these aspects in the parallel test of asynchronous working devices.
Armin
[...] the past couple of weeks, one, which I already blogged, has to do with Power-Aware ATE. Since I blogged it last, there have been some very interesting comments added. I plan to pass my take on those [...]
I posted the comment below in the Protocol Aware discussion under the Semiconductor Product, Test and DFT Engineering Linked group a couple of days ago but there have been no responses. Seemed like a good idea to post it here as well.
Protocol Aware (PA) ATE may have quietly disappeared at ITC 2008 but it is alive and well at ATE manufacturers (at least one). Teradyne presented a paper at the Beijing Advanced Semiconductor Technology Symposium (BASTS) last October with a clear message that PA will be a fundamental architectural shift in ATE.
In the spirit of full disclosure I wrote and delivered the paper with the full cooperation of Teradyne marketing and engineering organizations.
I am new to this group so if anyone is interested in the paper and associated presentation material please point me to the right place to post it.
I just noticed an interesting article in Electronics Weekly by Eric Starkloff from National Instruments. He mentions an increased demand for Protocol Aware ATE caused by complex SOC and SIP devices. I agree completely.
Regards
Eric Larson
Hi Eric:
Thanks for posting it here as well – I haven’t been lurking on LinkedIn in the last week or so – maybe because I got hooked on Facebooks Mafia Wars –
yikes. Anyway, I am always interested to read papers on emerging trends, especially w.r.t. DFT and Test.
And, I also saw that NI article, and I was planning on doing a follow-up post on PA test, because it seems to be an interesting topic for readers.
If you’d like me to post your paper, send it to me and I’ll call attention to it.
Thanks for reading!!
JMF
Hi Eric,
Could it be possible to share me a copy of your materials regarding PA? I am so interested
Bernie, sorry about the way late reply but I recently started a new job at Northrop Grumman and haven’t kept up with much on the Web.
You can find a copy of the publicly available PA material on my LinkedIn site. If you can’t find them please drop me an e-mail at larsonecl@gmail.com
Regards
Eric Larson
[...] opening the magazine, I found a couple more interesting articles on test as well, including one on Protocol-Aware ATE (although the term wasn’t used in the article). You can read the whole magazine at their [...]