Test Compression Series
I’d like to start a series of posts - they won’t necessarily be contiguous - on the use of test compression in design for test. The DFT job has gotten so much bigger in the last few years, and test compression is one of the most fundamentally different aspects of the expanding role.
I’d like to explore the different architectures being offered, the pros and cons, hopefully without turning the thread into an EDA pissing contest. I know what tool I’m using, but I’d like to discuss all the offerings in the hope of providing true design-for-test enlightenment for all those who read, and myself, of course.
If you deal in both DFT and multi-million gate ICs, this is a subject with which you should be familiar. The economics of test require it. Intuitively, it should be easy to grasp: Take the number stuck-at fault ATPG patterns you already have, and multiply by four. That’s about how many patterns you’ll have after adding transition fault ATPG vectors, and maybe some delay fault vectors. If you’re dealing in the high gate counts, that’s going to top out many top-of-the-line ATE pattern vector spaces - your results may vary. But I haven’t even mentioned BIST patterns or functional patterns… you get my drift?
But you don’t have to be designing mega-chips to want this technology - you may be just be short of device pins available for use as scan pins. So you only have a few pins? Well implementing a one scan chain test solution is not going to win you favors from the production team, who needs to achieve sub-second test times to squeeze out the last drop of margin.
So how does this work? Well this is going to be a series, but here’s the nutshell: test compression works by inserting logic in the scan chain paths that decompresses one or more scan data streams into many more parallel internal scan chains, and then compresses the scan results back into a narrow stream for comparison by the ATE. To be more clear, I’m going to need a picture, but that’s for another day.
Let me know your questions about test compression, ATPG, BIST, or any other design for test topic, and we’ll discuss it in this blog!
’til next time…
Stumble It!
[...] As I blogged a couple of days ago, I’d like to write a series of posts about test compression: what it is, why you’d want to use it, it’s many variations, who in the EDA-sphere offers tools to implement it, etc. [...]
[...] Test compression, as we’ve been discussing recently in parts 0, 1, 2, and 3 so far, is an excellent example where internal circuitry eases the requirements of the external tester. ATE tester memory requirements shot through the roof with at-speed scan requirements. A technology requiring the storage of much less test data for the same fault coverage logically follows. Actually, logic BIST falls in this category also, but that’s for another discussion. Here we explore just how much test compression buys you. [...]