DFT Digest

The 2009 International Test Conference was formally announced earlier this week.   In November, the conference makes its return to Austin, TX – site of ITC 2005, the first ITC held west of the Mississippi.   Now, normally I normally rifle through the advance program (which in a fit of green, I printed out 2 pages per side, and realized my eyes are way to old to actually read that!), and blog about what I think is interesting.

This year, I thought I’d poll some of the organizers of the event to see what piqued their interest in what they were planning for ITC this year.  Bill Eklow (Cisco), Program Chair, and and Scott Davidson (Sun), Marketing Vice Chair, were kind enough to share their thoughts.

One of the things that ITC has quietly let slip away is a conference theme.  As Eklow states,

“In the past few years we’ve stayed away from a central ‘theme’ for the conference. You can see that we have a very diverse program.”

As ITC’08 program chair Nur Touba says in this interview in T&M World, the 2008 committee decided not to have a theme.  In 2007 (the most recent year with a theme) it was Facing Nanometer-Technology Test Challenges. Well, with an area as diverse as DFT/Test, why try to narrow the interest, eh?

Eklow does point out that there are some prominent points in the program:

“…we have a very strong program for Mixed Signal/RF and ATE.  Several papers overlapped both areas to some extent and will be of interest to attendees from both areas [...] DFT was another area that got a lot of submissions this year and consequently more sessions. We’ve also got an embedded tutorial and panel session around Testing 3D chips which should be very interesting in that it combines elements of both board and chip test.”

3D chips… cool concept. One hears more and more about them these days. At ITC this year there is an embedded tutorial and a panel devoted to the subject. Are the techniques new? Are there existing methods to be applied?

Davidson’s interest is in trying to make sense of what comes back from the ATE:

“data that can show us subtle problems and which has helped us diagnose problems using statistics. So I’m looking forward to session 1 and some of session 4 especially, because they have some interesting papers on analyzing data.”

Another interesting subject for Davidson is test economics.

“I’ve been interested in test economics for a long time, ever since I had to justify my budget when I was at Bell Labs. We know we are saving our companies and our customers money, but sometimes it is hard to prove it, and it has always seemed that decisions on what type of DFT or test to use was not made entirely rationally.”

Davidson has been active in a group devoted to just that: the Testability Management Action Group (TMAG). Monday, November 2, Davidson, with fellow TMAG members, will offer a full day tutorial on the subject.

I’ve always considered ITC to be a week-long event, but it’s only that way because the conference itself is bounded by tutorials on the front end (Sunday and Monday) and workshops on the back end (Thursday and Friday). As Eklow puts it:

“The tutorials are a good way to get yourself ready for the program. The workshops are a good way to expand your horizons afterwards.”

Another aspect of ITC that I’ve always wondered about (ever since Ben Bennetts brought it up to me a couple years back) is the board-level test content (or lack thereof) of the conference. As an IC DFT engineer, I always feel deficient with respect to where my devices are eventually soldered down. I asked about the board-level content at this year’s ITC. Eklow, a board test engineer at Cisco responded:

“I think all of the embedded tutorials on Wednesday will be of interest to the Board/System test people in addition to the In-Circuit test session on Wednesday morning. There are also elements of board/system test that are “hidden” in Thursday sessions on “Getting Working Silicon” and “Post Silicon Test, Debug and Validation”. Couple that with open working group meetings for several boundary-scan based standards (IEEE P1149.8.1, IEEE P1687, IEEE P1581, IEEE 1149.6), and that makes for a pretty full schedule.”

So now we’re hiding the content (because PCB test guys are so clever)   Just kidding – I’m convinced.

Personally I’m looking forward to visiting Austin again, seeing old friends and acquaintances, making new ones. In the meantime, leading up to the conference, I will go find a better set of readers, figure out my schedule, and blog it.

What are you looking forward to?  Comment here, or e-mail me.  I’d like to know!