DFT Digest

In a couple of previous posts, here, and here, I started discussing different design-for-test tools - you know, other than your run-of-the-mill ATPG and BIST tools. In the last post, I talked about a couple of tools that are targeted for the RTL domain. Now I’d like to mention some DFT-related products that are meant for use after the arrival of silicon.

It’s true: one of the nastiest bottlenecks in getting from silicon to production is debug of any kind of test on the ATE. One of the decisions a company should make is whether it’s wise to invest in what I call a “DFT tester”. A DFT tester is a scaled down version of a full-blooded ATE (big iron) that can, many times, fit into one of those god-forsaken cubicles that most of us work in.

Renting time on big iron can cost up to $500/hr. Add in the cost of the test engineer’s time, and you’re talking big bucks to debug scan vectors. So, over time, it may be economical to pick up a DFT tester. If your device is a SoC - the specs will eventually drive you to the bigger testers. But the more tester you design onto the chip (which, as DFT people, we should aspire to), the more you can accomplish on a low-cost tester.

One of the aims of the desktop tester seems to be ease of use, and seamless interaction with DFT tools, especially ATPG tools. This is done by interacting with them through the use of IEEE 1450 STIL, a standardized test language, which was designed for interoperability between tools and testers. STIL is a component in the common test architecture promoted by the Semiconductor Test Consortium (STC) - which is driven by Advantest, the world’s largest ATE vendor, but supported by no others - well, that’s a whole other story.

What I meant to point out were a couple of companies that offer lower-cost ATE solutions and software to address this DFT tester market: Inovys and Teseda. Each company offers both hardware and software to address DFT and debug level test. Inovys offers more on the hardware side (the Ocelot series ranges from a 256 pin ‘Personal Ocelot’, to a more production-worthy Ocelot, with up to 1536 pins). Teseda offers its ‘V520 DFT-optimized engineering test platform’, which is a littler lighter on the specs. I don’t know what the relative costs for these machines are. Each company also will provide debug software - mostly geared toward structural test (read ATPG) debug, and are STIL-based.

Anybody have experience with these testers? I’d love to hear about it!