Top 10 Things I Want to See at ITC

A week from today (Tuesday) the conference part of ITC Test Week starts.  There are a lot of activities surrounding the whole event, and you can get a sense for whole deal if you peruse the ITC Advance Program.  Since none of you readers offered up your to do lists for ITC next week, I guess it’s up to me - so without furthur ado, here are the Top 10 Things John Wants to Check Out at ITC 2008, Dave Letterman style…

10) Workshop: I’m not staying fo a workshop this year, but if I was… I’d check out the ATE Vision 2020.  As a former Test Engineer, there are a lot of neat topics covered here that offer a good view of future (and present) ATE methodologies.  One of the more promising techniques, Absolute Predictive Test (APT) is still the holy grail…

9) Sessions: Here are just a few of the interesting sessions happening at ITC…

Session 2: Microprocessor Test. Here, there seem to be some good papers on Core Test, which is interesting to me. Testing many thing at once…

Session 6: Delay Testing and Chip Performance Maximization, which includes a paper on testing for small delay defects in multicore chips - small delay defects, still being talked about, even though I’ve been told lately by someone that the concept of small delay defects is a “complete red herring“…

Session 9: Power-Aware DFT methods - all three papers look interesting - a lot of power discussion at this conference, for an issue that some don’t believe is an issue…

Session 29/34: Test Standards I/II - More IEEE 1500 content, and advanced JTAG discussion.

8 ) Lecture: Lecture 4 - Elevator talks, from the advance program, “Elevator talks from eight test professors about the top test research areas, including reliability, FPGA based testers, new fault models and error tolerance.” Not yet known whether the talks will actually be given on an elevator…

7) Tutorial: If I were going to one, it would be Tutorial 9 - DFT Fundamentals for Digital Test - for those days when it seems I can’t do anything right… :-) but in all seriousness, with all the advanced material being presented and discussed at ITC, it’s good to see that someone is still thinking of the folks just getting started.  Design-for-Test needs to be continually encouraged from the ground up…  Along the same lines, there is Tutorial E2 - A Brief Overview of Mixed-Signal Production Test for the Beginner, given by Gordon Roberts of McGill University, a well known MS Test expert.

My second choice would have been IEEE 1500 - Building a Compliant Wrapper, but it has been canceled.

6) Invited Address: This Is a Test: How to Tell if DFT and Test Are Adding Value to Your Company, given by Jeff Rearick of AMD. As a DFT engineer, it’s always good to have weapons in one’s evangelical arsenal, because whether we like it or not, we’re all DFT evangelists

5) Panel: Panel 1 - Power-aware DFT―Do We Really Need It? Now this is a question I would not had thought needed to be asked, because it seems so intuitively obvious that the answer is “yes, we do”. But there must be some sort of devil hiding in the details, if the ITC organizers have devoted a panel discussion to it…

4) New DFT tools: Like Magma TalusATPG - oh wait…

3) Special Events: In my quest to procure as much free food as possible, there are a couple of special events held by the EDA vendors: on Monday evening, Synopsys holds its16th annual SIG event, wherein Ken Butler of TI hosts three different speakers, presumably talking about Synopsys DFT tools .  Tuesday lunch will be hosted by Mentor Graphics, where we will be learning about yield learning… and hoping to win the door prize!

2) The Octoberfest Party: What’s more fun than engineers and beer? Almost anything, I suppose, but who knows? Could be a good time…

1) Networking: Of course, this is a big reason to schlep up to Santa Clara next week - to see people I haven’t seen in a couple of years.  Looking forward to seeing you all!

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