DFT Digest

System on Chip design involves gathering functions from various sources: different teams, different vendors, doesn’t matter – there’s never enough documentation.  System on Chip test, especially as increasing amounts of functionality is embedded, can become an intractable problem very quickly.

The first impulse of a designer facing this situation is to provide test access to the embedded block by sharing functionality with externally available mission-mode pins. As you could imagine, this approach runs out of gas almost before the car leaves the station (topical reference.. eh?), especially in the current age of high-speed serial interfaces. Even if the pins are available, a full-breakout mode is not always possible, so some control pins may be relegated to register access only. Now all the tests that existed for the embedded IP need to be re-written to use the registers and the I/Os. This is just an example of the corner you can paint yourself into.

So how does one simplify the integration of various IP while retaining (and re-using) full test capability? Enter IEEE 1500 Core Test. The 1500 Test Access Mechanism (TAM) is a JTAG-like interface used to shift test data into a device to apply to an embedded core. In addition, provisions are made in the standard for parallel test access, or a combination of both serial and parallel. In any case, the test vectors of a 1500 enabled core are usable when the core stands alone or is embedded in an SoC. Just as in 1149.1 testing, you can use the 1500 boundary register to test the logic surrounding the core, as well as what’s inside. The core provider communicates the test configuration and procedures through a specification expressed in Core Test Language (CTL, also an IEEE standard, 1450.6).

So how do I know this? I’ve read The Core Test Wrapper Handbook: Rationale and Application of IEEE std. 1500. by Francisco da Silva, Teresa McLaurin, and Tom Waayers. The book explains the reasons behind the standard and walks the reader through a small simplified example, slowly building up the CTL code necessary to describe the test of an embedded core. It details the design of the different parts of the TAM: The wrapper boundary register (WBR), the instruction register (WIR), and the bypass register (WBY), all analogous to the 1149.1 structures, but with more flexibility to allow many different test configurations.

The book is written in a tutorial style, taking a step-by-step approach, explaining the parts of the solution, then developing the CTL code to describe it. By the time you reach the end of the book, you have a full-fledged CTL description of the core and it’s test mechanism.

The Core Test Wrapper Handbook is definitely not a casual read;  you have to try to see it through.  I blame this on the pages and pages of raw CTL that is incrementally built up throughout the book.  However, I think it was done purposely, since CTL is so important in communicating the test infrastructure of the wrapped core.  Near the end of the book there is a particularly engaging chapter on different ways of integrating 1500 wrapped cores in an SoC.

My only other comment would apply to the majority of technical book s on the market these days (and this won’t be the last time I mention it), but it’s expensive.  Anytime a book is listed for over $100, you’ve priced me out of the market.  Fortunately, I got a significant discount by going through Amazon’s alternative marketplace (you see the links on the books webpage, where it says “10 used and new from…)