DFT Digest

Just wanted to point to Sramana Mitra’s take on the merger.  One of the last paragraphs in the article brought up an interesting point:

Consolidation is a necessity for the ATE industry just as much as the EDA industry. In fact, a whole new layer of consolidation that bridges the design side and the test side is in order.

[the bolding above is mine]

Then she mentions “inserting ‘testers’ into the chip” (hello! DFT!), and the inevitable declining demand for high end testers, which reminds me of another recent ATE deal that I meant to bring up: Verigy acquires Inovys.  Now that’s fairly old news, but it ties in, because you can see that even the biggest of ‘big iron’ tester companies are investing in the DFT tester space.

My interest was piqued as much as anyone else when I saw the public outing of Cadence’s hostile bid for Mentor last week. But as a DFT guy trying to look objectively at how this might affect other DFT guys/girls, it doesn’t seem like a big deal (although if I listen very carefully, I might hear a collective snicker from the DFT-folk at Freescale, who were shoehorned into Cadence tools a couple of years ago after being a predominantly Mentor house for a long time). So I wasn’t going to even offer my opinion.

But then another deal came to light yesterday that for me, drove home the fact that I work for an industry that seems to be circling the wagons and huddling together to weather an economy that’s taken the wind out of most everybody’s sails. And since this is just on the other side of the DFT fence from EDA, I thought I’d blog it. The deal: a 50/50 merger between Credence and LTX, two ‘big iron’ ATE vendors, both distant trailing competitors in the semiconductor test market that is dominated by the test industry’s ‘big three’: Advantest, Teradyne and Verigy.  The move follows on the heels of Credence’s announcement last week that they sold a $5M piece of their automotive test business to Advantest.  Anything to make a couple bucks…

As in any merger or acquisition, the main reasons given for the merger with LTX are ROI improvements due to combining/slimming certain groups to reduce overhead, and to be able to present themselves as a bigger company supporting more facets of a diverse industry. But just as in the Cadence/Mentor possibility, the interesting speculation is in the product ‘overlap’ (as in the Chris Edwards analysis of ‘Cadentor’), or product ‘rationalization’ as it’s termed by Rick Nelson of T&M World, in this blog post.

The big question is, will it keep them both afloat? The combined value of these two companies (if I read the Yahoo financials correctly) combined will still be ~20% of the smallest of the ‘big three’. And the ATE business is every bit as brutal as EDA… maybe it was a big deal for Cadence to pull out of DAC this year, but most of the ‘big iron’ ATE companies pulled out of ITC some years ago.

Oh yeah, and he new company’s name?  I got nothing. Submissions?

Please…

Two items from the news this past week (presumably timed to coincide with Semicon Japan):

First, it was announced Tuesday that Asset Intertech, who provides boundary scan solutions, acquired Intertest Tech (ITT), an Irish supplier of process emulation technology. This seems to be a cementing of the strategic relationship they’ve had for the past three years, which is targeted toward greater functional coverage using JTAG and CPU emulation for both structural and functional testing of PCBs.

Then, just announced today, Verigy (formerly, Agilent, formerly HP), a ‘big iron’ ATE company, has signed a deal to acquire Inovys, who offers ‘DFT Testers’, such as the Ocelot, Ocelot ZFP and Personal Ocelot. This is an interesting turn of events, given that Advantest (another ‘big iron’ ATE company) recently announced their T2000 tester, which claims to cut the cost of test in half.

My first thought is that it seems that in a tight semiconductor market, the test companies are circling the wagons and working together, a la Asset+ITT and Verigy+Inovys.

My second thought, regarding the IC ATE announcements (in conjunction with other articles that have appeared in the recent past), is that perhaps we’ll be seeing more ATE vendors crawling over toward standards-based systems, after years of resistance. At least with the DFT-class testers - most DFT testers are standards-based testers.

Anybody else have a take on this?

In a couple of previous posts, here, and here, I started discussing different design-for-test tools - you know, other than your run-of-the-mill ATPG and BIST tools. In the last post, I talked about a couple of tools that are targeted for the RTL domain. Now I’d like to mention some DFT-related products that are meant for use after the arrival of silicon.

It’s true: one of the nastiest bottlenecks in getting from silicon to production is debug of any kind of test on the ATE. One of the decisions a company should make is whether it’s wise to invest in what I call a “DFT tester”. A DFT tester is a scaled down version of a full-blooded ATE (big iron) that can, many times, fit into one of those god-forsaken cubicles that most of us work in.

Renting time on big iron can cost up to $500/hr. Add in the cost of the test engineer’s time, and you’re talking big bucks to debug scan vectors. So, over time, it may be economical to pick up a DFT tester. If your device is a SoC - the specs will eventually drive you to the bigger testers. But the more tester you design onto the chip (which, as DFT people, we should aspire to), the more you can accomplish on a low-cost tester.

One of the aims of the desktop tester seems to be ease of use, and seamless interaction with DFT tools, especially ATPG tools. This is done by interacting with them through the use of IEEE 1450 STIL, a standardized test language, which was designed for interoperability between tools and testers. STIL is a component in the common test architecture promoted by the Semiconductor Test Consortium (STC) - which is driven by Advantest, the world’s largest ATE vendor, but supported by no others - well, that’s a whole other story.

What I meant to point out were a couple of companies that offer lower-cost ATE solutions and software to address this DFT tester market: Inovys and Teseda. Each company offers both hardware and software to address DFT and debug level test. Inovys offers more on the hardware side (the Ocelot series ranges from a 256 pin ‘Personal Ocelot’, to a more production-worthy Ocelot, with up to 1536 pins). Teseda offers its ‘V520 DFT-optimized engineering test platform’, which is a littler lighter on the specs. I don’t know what the relative costs for these machines are. Each company also will provide debug software - mostly geared toward structural test (read ATPG) debug, and are STIL-based.

Anybody have experience with these testers? I’d love to hear about it!

Just a short note this afternoon, after 5 hours of trying to make head or tail of some pattern failures on the tester. The message is: DFT and design engineers, spend some time on the tester! It will open your eyes to the pain experienced by test engineers, caused by your lack of communication or attention to detail, or both. Oh yeah, it’ll also make you realize that certain ATE developers have not yet started developing software reliable enough to be classified as “modern”. But that’s another story.

Anyway, I’m not trying to be a hardass (after all, I’m dissing myself here), but it’s a fact: if you’re passing vectors to a test engineer, who has relatively little knowledge of the chips internals compared to you, if you don’t disposition every device pin as “important” or “mask out”, you will very likely get test vectors shoved back in your face.

The reason is that most of us write simulations with very narrow purpose. So “good” results are normally based upon the behavior of very few pins. The rest of the pins are “don’t care” to you, but happily translated into relevant, strobe-able, events in the test pattern.

If you deal with large ICs, it’s very likely that you don’t even have all the physically accurate models contained in the testbench you’re simulating. What do you care if the real processor’s in there? You’re writing a simple boundary scan test! Your JTAG works, but the processor interfaces are all screwy.

The other thing that was triggered in my mind as I was fighting the ATE today: I must, with every design for test trick available, make sure that the next chip can be tested on a much, much simpler tester.

Have a great weekend!