DFT Digest

Update: I could swear I published this article with a title, but then I noticed it coming up blank in my feed…

All along I’ve said that DAC’s not really my show, but it was more interesting this year, given the whole EDA Bloggers Birds of Feather deal. It inspired some good discussion, and I hope it becomes a repeated occurrence as we, the independent bloggers establish our value in the EDA community.

However, as I mentioned in a previous post, in my short walk about the floor, besides noting the distinct lack of ATPG in the Magma booth, I did have a couple of enjoyable conversations with some test-related exhibitors.

First, I talked to the guys in the WinterLogic booth. This was the first year at DAC for WinterLogic. Not quite a ‘household’ name in DFT circles, this company markets a product called Z01X, which is a “high-speed functional fault simulator for Verilog designs.”   Now, obtaining coverage by fault simulation, as a matter of practice for functional vectors, has taken a back seat in recent years to to the coverage achieved with structural methods (scan and BIST). But structural fault coverage is never a complete solution for the contemporary SoC, so the structural test-suite almost always has to be augmented with functional patterns.

Now the last time I actually used a fault simulator, nobody was talking about transition delay faults or bridge faults, but current fault simulators (I’ll go out on a limb here and say there are two: SynTest’s TurboFault and Z01X) cover both those classes of faults, and claim performance improvements and other added capabilities over previous generations of fault grading software.

One of the ways in which the folks at WinterLogic do believe they are unique is in their “test ordering and redundant test elimination capabilities“.  Z01X performs testability analysis on the design with respect to each test, then starting with the best coverage test, ranks and reorders the remaining tests after each run.  They claim to be able to reduce the overall test-set by as much as 50%.

This job of test optimization is many times tackled by the test or product engineer after a device has been in production to optimize test time. The decision to reorder or eliminate tests is based upon the statistics of how often particular tests catch defective parts, determined over time by testing many devices.  I’m sure a priori test selection in the pre-silicon domain by relative fault coverage is practiced also, in an ad hoc fashion, but Z01X would be the first productization of this as applied to functional pattern sets (ATPG tools also have this capability built-in, for structural patterns).

The folks in the Winterlogic DAC booth claimed to have produced excellent results with some very big customers with this technology.  After talking with them, I shuffled to the right (to the next booth) where TSSI was set up.  I’ll talk more about that in my next post, as well as my conversations with SynTest, Genesys TestWare, and LogicVision.

Stay tuned…

Now let’s face it: Design for Manufacturing (DFM) is the hottest sector of the EDA industry. Everything else is, well, meh. From what I can gather, there are those who feel the sector of the future should be ESL, but it’s my opinion that true system-level design is many years out. Let designers get accustomed to SystemVerilog, I say. DFM, on the other hand is an immediate need. It cuts to the bottom line of profitability for every semiconductor company pursuing leading edge products. These are problems the industry needs to solve.

I started writing this post a few days ago, and let it lie as a near casualty in my recent fight with blogging burn-out. In the mean-time, John Busco wrote a post on Sramana Mitra’s contention that DFM/DFY provider PDF Solutions needs to find an eligible EDA company (or vice versa) for company nuptials. John wonders just how big the DFM sector can get, when it’s main customers are fabs and big IP providers. That’s a good point.

But I still contend that this sector is crucial to semiconductor companies, fabless or not. Very few chips, without it, will make it out of the fab alive. And that’s no way to run a chip business. So maybe Sramana is right - DFM/DFY companies need to be hooked up with EDA vendors as part of their portfolio. The business model should be different in that the actual benefactors (chip companies) will be using the tool, through the tool owner (the fab) - unless the chip company is big enough and pushes enough volume to warrant having their own tool. I rent my ski equipment, if you get the analogy.

So what does this have to do with Design-for Testability? I’ve mentioned a few times that DFT/Test are essential to a successful DFM strategy. It should be obvious - I mean, without a feedback mechanism, and data collection, how can yield be improved?

In a new article: DFT, ATE drive yield improvement, in T&M World written by Ajay Khoche of Verigy and Wu Yang of Mentor, the benefits and challenges of leveraging structural test results by linking them back to the design itself. The EDA industry is actively working to create these linkages - companies that provide yield analysis tools should be able to take scan failure data and attempt to automatically isolate the failing circuitry in the schematic, and ultimately, the layout. Yet another reason for DFM/DFY tools to be part of a EDA vendor’s portfolio, because, as of now, standard linkages are not yet in place.

An ‘advisory’ group that is… somehow DFT religion must be brought to upper management.

Introducing the Testability Management Advisory Group (TMAG), “a grass roots organization made up of test professionals who believe that success for Testability in general, and Design for Testability (DFT) in particular, requires the involvement of management at all levels.”

The first official meeting of TMAG will be held December 10th, from 9:30-11AM in San Jose, in conjunction with the IPC Test and Inspection Conference. One can attend personally, or by WebEx.

The motivation for the TMAG is the apparent lack of support from non-technical, and upper management for DFT efforts. The subject has been addressed prominently during panels at the last two AutoTestCon gatherings.

I think most every DFT professional has dealt with resistance on some level from designers, design managers, project managers, on up the line. I myself was told one time by a project manager not to speak to his designers anymore, because I was ‘confusing them’. Why DFT was confusing to a bunch of designers is a subject for another time, but the point is, we’ve all faced it.

Louis Ungar of A.T.E. Solutions is organizing this meeting, and hoping for participation from not only DFT and Test personnel, but from non-technical management as well, to help define and document Design-for-Test best practices and clear cost/benefit analysis tools to help crystallize the advantages of supporting the DFT effort.

For questions about this group and/or event, please contact Louis at LouisUngar@ieee.org

This is DFT Digest, so we talk about Design-for-Test a lot. Makes sense, right? But the International Test Conference is not just DFT, in fact it’s really mostly Test. As much as we DFTers want to bring the tester into the chip, the fact is that it doesn’t always make it. And tons of great research and development goes into test technology and methodology to be able to evaluate the biggest and fastest chips and boards that we can conjure up.

I’ve tried to gather feedback from friends who attended and participated in ITC this year. One who has offered his pre-show as well as post-show insights is Ken Butler of Texas Instruments. Here’s some of what he said about his week:

• Someone said that Adaptive Test turned out to be a de facto theme and I guess I would tend to agree. The three major players in this space (Optimal Test, Pintail, and Test Advantage) were all out in force on the exhibits floor.
• Seems like scan chain debug is growing in importance - There were several papers on that subject.
• There were more reliability papers this year than in past years. Timing and at-speed topics were well-represented.
• A few papers on logic BIST, again maybe a slight resurgence.
• Ben Bennetts did an entertaining look at the history of test from back in the 50’s to the present as part of his swan song as he retires.

Ken Butler is a TI fellow, and works in the product reliability group, on development of outlier techniques, and test quality modeling. He gave the first in a series of invited addresses at ITC this year, called Pinning down this elusive thing called ‘adaptive test’. These are fascinating topics, especially when you’re working for a company that produces and tests millions of devices per month. Cutting the cost of test, while maintaining quality can mean the difference between profits and losses. Design for test is just one way to accomplish that. By tracking and studying process variations and how they affect the outcome of test, the test itself can be optimized, and adapted, to provide the best quality with minimal cost.

So many interesting topics, so little time…

How much is enough? I mean, the more the better right? Shorter test time, fewer I/Os needed, what’s not to like about that?

If you were at ITC last year, and you were clued in on device-level design for test issues as I was, you may have noticed that both Mentor and Synopsys came up with papers addressing this issue. Interestingly enough, it seeemed they were coming from completely opposite points.

Chris Allsup from Synopsys brought the paper entitled The Economics of Implementing Scan Compression to Reduce Test Data Volume and Test Application Time.

Janusz Rajski of Mentor, et. al., presented a paper that describes a new test compression architecture, entitled X-press Compactor or 1000x Reduction of Test Data.

If you missed them, related articles have appeared at Test & Measurement World Online: The Mentor article called simply, Test Compression, and the Synopsys called Optimizing Compression in Scan-based ATPG DFT Implementations.

So now that you’ve clicked on the links and thoroughly read and considered each article, what do you think?  Do they argue opposite points?  Leave a comment below and tell me.

My take is after the click.. (more…)