DFT Digest

Now let’s face it: Design for Manufacturing (DFM) is the hottest sector of the EDA industry. Everything else is, well, meh. From what I can gather, there are those who feel the sector of the future should be ESL, but it’s my opinion that true system-level design is many years out. Let designers get accustomed to SystemVerilog, I say. DFM, on the other hand is an immediate need. It cuts to the bottom line of profitability for every semiconductor company pursuing leading edge products. These are problems the industry needs to solve.

I started writing this post a few days ago, and let it lie as a near casualty in my recent fight with blogging burn-out. In the mean-time, John Busco wrote a post on Sramana Mitra’s contention that DFM/DFY provider PDF Solutions needs to find an eligible EDA company (or vice versa) for company nuptials. John wonders just how big the DFM sector can get, when it’s main customers are fabs and big IP providers. That’s a good point.

But I still contend that this sector is crucial to semiconductor companies, fabless or not. Very few chips, without it, will make it out of the fab alive. And that’s no way to run a chip business. So maybe Sramana is right - DFM/DFY companies need to be hooked up with EDA vendors as part of their portfolio. The business model should be different in that the actual benefactors (chip companies) will be using the tool, through the tool owner (the fab) - unless the chip company is big enough and pushes enough volume to warrant having their own tool. I rent my ski equipment, if you get the analogy.

So what does this have to do with Design-for Testability? I’ve mentioned a few times that DFT/Test are essential to a successful DFM strategy. It should be obvious - I mean, without a feedback mechanism, and data collection, how can yield be improved?

In a new article: DFT, ATE drive yield improvement, in T&M World written by Ajay Khoche of Verigy and Wu Yang of Mentor, the benefits and challenges of leveraging structural test results by linking them back to the design itself. The EDA industry is actively working to create these linkages - companies that provide yield analysis tools should be able to take scan failure data and attempt to automatically isolate the failing circuitry in the schematic, and ultimately, the layout. Yet another reason for DFM/DFY tools to be part of a EDA vendor’s portfolio, because, as of now, standard linkages are not yet in place.

TGIF Folks! Some of you are still milling about Santa Clara, possibly attending one of the workshops. Others have packed it in and gone back to work. And me, I’m still chained to this workstation… so if you went to ITC, it was, by default, better for you than for me!

There are three workshops this year: DFM&Y (Design for Manufacturability and Yield), which is the more “design” part of test, DBT (Defect-based Test), which is more “test”, and ATE Vision 2020, where people will either be talking about test in the year 2020 or sharpening their vision (to 20/20) of the future of test in general, depending upon who you talk to. Something for everyone here.

Speaking of DFM, panel 4 on Wednesday explored Test’s role in DFM (Does Test Have a Greater Role to Play in the DFM Process?). Tets Maniwa wrote about it in an article at EE Times here. This is a subject that I’ve wondered about in a few different posts when DFT Digest first started. Just do a search for DFM. And you’ll see the subject has come up. It’s good to see DFM being discussed at ITC.

I’ve gotten some feedback on the conference this week, so I’ll be posting regularly to discuss some the more interesting papers, panels and addresses. I invite all you readers to get me your feedback, either by commenting here, or e-mail me at jford@dftdigest.com!

In my DAC and DFT - post #2, I linked to an article at Test & Measurement World, that briefly outlined a few different ‘new’ DFT technologies being pursued by the big EDA companies. One of these areas was termed volume diagnostics or defect diagnostics. This ‘new technology’, to me at least, is more DFM than DFT, but I’ve said from the beginnings of this blog that DFT has an important part to play in this new acronym.

The concept behind this is that data collected during test, especially scan test (ATPG), can be used to track down problems - in the layout. As I poke around the online information, I get the feeling that defect diagnostics refers to the ability to import test (ATPG) data into a physical design environment and locate the probable site of a defect. Volume diagnostics, I think, refers to the same thing on a larger scale - in other words going from failure analysis to yield analysis, or going from analyzing a possibly random defect to a systematic defect, that may be present due to the way the IC was designed and laid out.

This data collection is the subject of an open meeting of the STDF Fail Data Standardization group at Semicon West next week.

(more…)

It was an offbeat announcement, I thought, when I saw Synopsys’ press release stating they had hit the top500. Number 242 in the top 500 fastest supercomputers that is…

So, since when are EDA companies in the business of creating teraflop computers? Especially wheen they’re constantly engaged in making their software faster. But there it is, all you need are 329 linux servers all hooked up with 1GB ethernet, and you’re ready to take on your next big design (oh yeah, and unlimited licenses!).

None of the articles about the Synopsys screamer mentioned which software was being run, but then this blog post over at Mike Santarini’s blog on EDN shed a little light on why all the EDA compute power might be needed. Mentor is teaming up with supercompter specialists Mercury Computer Systems and IBM on their new offering in nm-scale OPC.

So the mass of data has become too massive for for your garden variety linux pool. You now need a supercomputer!

help…

I’ve just been searching around for DFM related material, and I keep seeing DFT being mentioned as a critical component of DFM, so I’ll just keep on mentioning it here.

The latest article I find (and I guess it’s not new, but it’s dated 7/6/2006, which is new enough) is by Ron Wilson at EDN, and it contains a sidebar on DFT and DFM, but from a different angle than what I blogged on yesterday (i.e., test as measurement/analysis). This piece discussed it more from the notion that design-for-test must be planned and executed, keeping in mind the systematic process variations that will screw the designer if he/she does not consider DFM.

Citing a marketing head for LogicVision, the article noted that “IR drops can be significantly smaller than they would be during sustained operation of the same circuit. So, the one-shot test may miss a delay fault that is IR-drop-related simply because launching one edge didn’t sufficiently stress the supply grid.” Which is probably a very good point. As you might expect, LogicVision claims to have a tool that creates patterns that mitigate the issue.

The other significant point, IMHO, related to the fact that failure modes are changing with geometry shrinkage, but fault modeling technology is not keeping up. It would be nice to be able to utilize a predictive DFT methodology that uses analysis of both the layout and timing models to come up with a more efficient test set.

Hmmm… maybe soon?