DFT Digest

Two items from the news this past week (presumably timed to coincide with Semicon Japan):

First, it was announced Tuesday that Asset Intertech, who provides boundary scan solutions, acquired Intertest Tech (ITT), an Irish supplier of process emulation technology. This seems to be a cementing of the strategic relationship they’ve had for the past three years, which is targeted toward greater functional coverage using JTAG and CPU emulation for both structural and functional testing of PCBs.

Then, just announced today, Verigy (formerly, Agilent, formerly HP), a ‘big iron’ ATE company, has signed a deal to acquire Inovys, who offers ‘DFT Testers’, such as the Ocelot, Ocelot ZFP and Personal Ocelot. This is an interesting turn of events, given that Advantest (another ‘big iron’ ATE company) recently announced their T2000 tester, which claims to cut the cost of test in half.

My first thought is that it seems that in a tight semiconductor market, the test companies are circling the wagons and working together, a la Asset+ITT and Verigy+Inovys.

My second thought, regarding the IC ATE announcements (in conjunction with other articles that have appeared in the recent past), is that perhaps we’ll be seeing more ATE vendors crawling over toward standards-based systems, after years of resistance. At least with the DFT-class testers - most DFT testers are standards-based testers.

Anybody else have a take on this?

A few days ago I wrote a plaintive post about an article I came across somewhere out there on the net, with the title “Dot 6 Explained”. Amazingly enough, the author of that article, James Stanbridge of JTAG Technologies replied to my post corroborating the obvious fact that it had been ‘edited’, and agreed to provide me with the full article, including ‘box-outs’ and figures.

So, if you’re interested, I’ve got it here in pdf format. I included the discarded diagrams, and the article reads much better, and is a nice introduction to the technology. I’d like to do some more discussion on the subject, simply because I’d like to learn more about it, so stay tuned for that.

Give it a read!

I’ve been trying to put together some info about JTAG and boundary scan, but being a chip engineer, I’m having a hard time expanding my mind to the edges of the device lately. However, this item came across my e-mail this week - a free, expanded version (110 pages) of Asset Intertech’s Boundary Scan Tutorial.

You must register to get it sent to you, but it’s FREE ( from experience, I know that word FREE is a huge magnet for engineers, most especially when it precedes FOOD )

As I was at their website signing up for the book, I found, on the same page, links to some great material on boundary scan DFT from both chip and board-level perspectives, developed by Ben Bennetts. Dr. Bennetts retired this year, but his legacy lives on in this great material! Go check it out! Lot’s of information on the many facets of boundary scan ind it’s applications. I wish all EDA vendors had this type of educational content available to the public. Our DFT engineers, more often than not, are not getting this in school.

Alright Asset, I’m waiting by my mail box…

Today I received an e-mail from Dr. Ben Bennetts, DFT Consultant (Semi-retired) with a great introduction to some ‘in-the-works‘ extensions to the IEEE 1149.1 test access standard, called IJTAG (Internal JTAG) and SJTAG (System JTAG).

The Internal JTAG effort seeks to standardize the access to ‘internal instruments’ of all sorts that may reside on a single chip. IJTAG has been given permission to work on the standard by the IEEE as P1687.

The SJTAG effort deals with extending test access across several boards, perhaps joined through a backplane, and may include much more functionality than just board-level test, such as system-level configuration.

Much more detail is available in a PDF write-up titled IEEE Testability Standards: Recent Developments, graciously provided by Dr. Bennetts. Please take a look!

If you have questions, you may contact Dr. Bennetts directly, or just comment below, and we will pass it along…

I mentioned in another post just after ITC 2006, that I’d met Ben Bennetts for the first time. We had breakfast, and talked a bit about this blog I was trying to start up. It was an introductory conversation, but secretly, I was hoping to eventually convince him to work up some material on JTAG for the blog. In the end, I’d like to get plenty of contributed material to appear in this blog. Information from the masters of DFT to the masses. That’s what I’m aiming for!

As for Dr. Bennetts, this being his last year before retiring, he’s pretty busy. But he thought the blog was a good idea, and wanted me to make sure to do plenty on board-level test while I was at it. So far, I’ve failed at that. But eventually, I’d like to do some more reading, and be able to put together something coherent.

He also talked some about how over he years he’s pushed very hard to get board-level tracks included in the ITC program. It seemed that device-level issues dominated the space. He pointed out to me that there is plenty going on with board-level test, and standards are currently being worked on to expand the technology of IEEE 1149.1 to new levels, including both the system level (SJTAG), and at the other end, inside the device (IJTAG).

My new friends over at design-for-test.com have also been recipients of Dr. Bennett’s promotional efforts. They have a whole table of the different JTAG standards activities. Hop on over and see it.

Meanwhile, I have some reading to do…