Last notes from DAC, then back to DFT (part 1)
Update: I could swear I published this article with a title, but then I noticed it coming up blank in my feed…
All along I’ve said that DAC’s not really my show, but it was more interesting this year, given the whole EDA Bloggers Birds of Feather deal. It inspired some good discussion, and I hope it becomes a repeated occurrence as we, the independent bloggers establish our value in the EDA community.
However, as I mentioned in a previous post, in my short walk about the floor, besides noting the distinct lack of ATPG in the Magma booth, I did have a couple of enjoyable conversations with some test-related exhibitors.
First, I talked to the guys in the WinterLogic booth. This was the first year at DAC for WinterLogic. Not quite a ‘household’ name in DFT circles, this company markets a product called Z01X, which is a “high-speed functional fault simulator for Verilog designs.” Now, obtaining coverage by fault simulation, as a matter of practice for functional vectors, has taken a back seat in recent years to to the coverage achieved with structural methods (scan and BIST). But structural fault coverage is never a complete solution for the contemporary SoC, so the structural test-suite almost always has to be augmented with functional patterns.
Now the last time I actually used a fault simulator, nobody was talking about transition delay faults or bridge faults, but current fault simulators (I’ll go out on a limb here and say there are two: SynTest’s TurboFault and Z01X) cover both those classes of faults, and claim performance improvements and other added capabilities over previous generations of fault grading software.
One of the ways in which the folks at WinterLogic do believe they are unique is in their “test ordering and redundant test elimination capabilities“. Z01X performs testability analysis on the design with respect to each test, then starting with the best coverage test, ranks and reorders the remaining tests after each run. They claim to be able to reduce the overall test-set by as much as 50%.
This job of test optimization is many times tackled by the test or product engineer after a device has been in production to optimize test time. The decision to reorder or eliminate tests is based upon the statistics of how often particular tests catch defective parts, determined over time by testing many devices. I’m sure a priori test selection in the pre-silicon domain by relative fault coverage is practiced also, in an ad hoc fashion, but Z01X would be the first productization of this as applied to functional pattern sets (ATPG tools also have this capability built-in, for structural patterns).
The folks in the Winterlogic DAC booth claimed to have produced excellent results with some very big customers with this technology. After talking with them, I shuffled to the right (to the next booth) where TSSI was set up. I’ll talk more about that in my next post, as well as my conversations with SynTest, Genesys TestWare, and LogicVision.
Stay tuned…
