DFT Digest

Very funny - EDN’s blogger Margery Conner posts that today is ‘Pi’ day (March 14th, a.k.a 3/14, 3.14, pi).

Editor Rick Nelson points out that they can’t observe Pi day in Europe, since they write their dates differently (14/3/2008).

Then of course, someone has to say that they guess that makes it American Pi day - hee hee!

I was reading Peggy Aycinena’s DVCON post at EDACafe this past week, and ran across a couple of thought provoking (at least for me) paragraphs. Ms. Aycinena was describing the Wednesday keynote speech given by Wally Rhines of Mentor. He opened his talk with a discussion of DFT. I’m reproducing most of the DFT part, and only a portion of his verification discussion, for brevity:

…He said on-chip complexity forced folks to search for better ways to test over the years. Bigger and faster computers had helped, as had testing for stuck-at faults, but the number of transition faults still got bigger. Test engineers beat that stuff back, Rhines said, by shifting to scan-based test, by introducing ATPG, BIST, and ordered-test patterns, and had increased test efficiencies by up to 10x. But it wasn’t enough because even though the cost of components came down, the cost of test did not.

Then in 2001, Rhines said Mentor’s DFT guru Janus Rajski came up with a new approach based on the theory that folks should stop testing what they’ve already tested. Rhines said implementation of the algorithms behind on Rajski’s theory, in combination with test-data compression, has increased test capability 100x and will increase that capability 1000x in the next 5 years. He concluded, “We moved from a mode where we added more cycles of test, to a mode where we added more test per cycle.

Rhines moved on to verification and reiterated what everyone knows – except those who’ve been on a different planet for the least 10 years – verification costs more than design, and that’s way, way too much. [snip - and Rhines says] “I believe that there’s something out there that will do for verification what test-data compression did for test,

So how about that? For so many years, test borrowed from verification, in that functional patterns originally used for verification were re-targeted to the ATE to screen parts. Advances in DFT methodology, from necessity, made huge gains in efficiency by looking at the problem structurally. Now verification, painfully expensive and time consuming, could benefit from the same kind of innovation.

Any ideas out there? There’s money to be made….

Just saw this over at DeepChip:

  Did you hear Mike Santarini of EDN just got laid off on Friday??

  This means the 3 biggest independents (Gartner/EETimes/EDN) that

  used to cover EDA have pretty much killed off their EDA coverage.

  Cadence stock is crashing.  Fewer young faces do chip design now.

  Are we watching the EDA industry collapsing in a self-inflicted

  implosion?  Is there a way out or should people working in EDA

  now start studying to pass the California realtor's license exam?

First Smith, then Goering, now Santarini? So where shall we find independent, in-depth coverage of EDA issues? Is it “every man for himself” when it comes to EDA tools? Maybe the EDA industry feels we’re all better off believing their press releases?

Believe me, DFT was/is rarely covered by any of these sources anyway,  but it seems to me to be a concern for the integrity of the industry as a whole.

What do you think?

Check out this top 10 list (h/t Maggies Farm) from the acknowledged creator of the term ‘weblogs’, Jorn Barger - indispensible advice for new bloggers (which I’m sure applies to all bloggers). Interestingly enough, his concept of a blog lines up more with a site like del.icio.us than with any of the most popular blogging platforms such as Blogger, Wordpress, etc., which is reflected in his rule #2:

2. You can certainly include links to your original thoughts, posted elsewhere … but if you have more original posts than links, you probably need to learn some humility.

So where does that leave us? I can certainly relate to the humility lesson. Even though I do try to create original content, because I think it will attract readers, I also try to always credit my sources, and link to content that supplements my material, because more than anyone else, I know what I don’t know, which is plenty.

Personally, I found the list to be helpful - I like numbers 9-10, which may help to aggregate more high quality DFT content for me to post (I do some aggregation of DFT News already - at my Blogger account).

On more thing. After checking out the picture, I think Mr. Barger belongs in the Motley Crew that John Busco blogged about last week!

An ‘advisory’ group that is… somehow DFT religion must be brought to upper management.

Introducing the Testability Management Advisory Group (TMAG), “a grass roots organization made up of test professionals who believe that success for Testability in general, and Design for Testability (DFT) in particular, requires the involvement of management at all levels.”

The first official meeting of TMAG will be held December 10th, from 9:30-11AM in San Jose, in conjunction with the IPC Test and Inspection Conference. One can attend personally, or by WebEx.

The motivation for the TMAG is the apparent lack of support from non-technical, and upper management for DFT efforts. The subject has been addressed prominently during panels at the last two AutoTestCon gatherings.

I think most every DFT professional has dealt with resistance on some level from designers, design managers, project managers, on up the line. I myself was told one time by a project manager not to speak to his designers anymore, because I was ‘confusing them’. Why DFT was confusing to a bunch of designers is a subject for another time, but the point is, we’ve all faced it.

Louis Ungar of A.T.E. Solutions is organizing this meeting, and hoping for participation from not only DFT and Test personnel, but from non-technical management as well, to help define and document Design-for-Test best practices and clear cost/benefit analysis tools to help crystallize the advantages of supporting the DFT effort.

For questions about this group and/or event, please contact Louis at LouisUngar@ieee.org