DFT Digest

One of the announcements from Test Week’s onslaught of test-related press releases from EDA vendors was Magma’s roll-out of Talus ATPG and Talus ATPG-X.   A couple of interesting things about this product:

1)  Its tight integration into the Talus toolset means that it is a Magma user’s tool only.  So Magma is marketing it to about a third (?) of the total available ATPG market.

2) Its both multi-threaded and distributed - which are probably both necessary given the fact that the tool is tapping into the physical database to target multiple fault models concurrently (this was Siyad’s first comment when we were discussing the announcement).

3) It uses a ’stateless broadcaster’ and compactor for test data compression, for a ~40X compression capability.  This is similar to Synopsys’ DFT MAX compression.  There are other similarities as pointed out in this post at The Tao of ASICs (amongst them, a prime example of synchronicity related to multiple fault detection using one pattern, including reordering of patterns based on fault type) .  The Tao is declaring it a “DFT Arms Race”.

Talus ATPG and ATPG-X are placed right in the sweet spot of current ATPG development - links to the physical database and detection of multiple fault types.  We’ll be interested to see how this plays out.

Coming up later this week we’ll discuss more of last week’s announcements.

Remember way back, this time last year, there were rumors about that Magma had abandoned their design-for-test tools?  First, there was a post over at DeepChip,  about the cancellation of their test program.  Less than a week later, Richard Goering at EE Times wrote an article stating that, according to Magma marketing folk, Magma did indeed drop out of the BIST market, but was working on an ATPG offering (which was “in alpha stage”).

That was shortly before ITC last year, and when I asked about it at their booth, people looked at me as if they didn’t know what I was talking about (I guess they don’t talk about these things to just anybody - that’s OK).

Well, today, Magma announced  Talus ATPG, and Talus ATPG-X, for ATPG and test compression, which are integrated into their physical suite, and claimed to be the only truly physically aware ATPG implementation.   Other claims include multi-threaded operation, and concurrent targeting of multiple fault models.  The press release included comments from two companies that have seen the product: IDT and Comtech AHA.

Anybody else out there seen the product?  Let me know what you think.  Is ATPG becoming a commodity (everyone offers it)?

I don’t know if I ever mentioned it before, but a DFT blog was not my original objective for creating an IC design oriented website. In truth, a couple of buddies and I had visions of a well-oiled EDA forum site with experienced professionals trading tricks of the trade – I was just going to be the design for test moderator. But, as always, engineers get busy or distracted, and well, we haven’t pulled it off yet.

However, there are other websites with forums out there. A couple come to mind: design-for-test.com (this would be my preferred place to post a DFT question, as it’s run by an expert), edaboard.com, and edacafe.com also has a forum. One thing about these forums – it seems DFT still remains somewhat an esoteric art. Some of the questions: “Why DFT?”, “What is DFT?”, or “Please state all the DFT design rules and their solutions…”

Once again, design for test is often lobbed to a junior member of the design team, who more often than not, has no idea where to start. And since a majority of our engineering schools spend next to no time on test, well, here we are.

Dave Letterman counts down from 10 to 1, but I’m pretty much a bigendian digital DFT engineer, so I’m going from 9 to 0. So without further ado, I present to you my ‘Top 10 Scan Design Rules’:

9 - Melting pot: NOT! don’t mix scan cell types in a design
8 - Primary input controlled resets
7 - Primary input controlled clocks
6 - Fight the scourge of internal tri-state busses
5 - Mixing clocks and data is racy
4 - Avoid combinational feedback
3 - Remember your memories
2 - Proceed with caution (from one clock domain to another)
1 - Know your ATE
0 - Scan everything

The longer winded explanations are after the click. Have a read, and let me know what you think! (more…)

Another article, this by Sanjiv Teneja of Cadence Design Systems, promoting DWT, or “Design-With-Test” has been posted over at Test & Measurement, as a guest commentary. I blogged a few weeks ago about a similar article by another marketing man from the same company. I smell a conspiracy! Just kidding, go to DeepChip for conspiracies.

Tomato, tomahto, DFT, DWT - the point is clear: Design-for-Test is not what it used to be.  Some of the areas touched on in this article were:

• Power concerns with ATPG and test compression
• Routing congestion concerns with test compression
• Improved defect coverage through timing aware
• Physical awareness during all embedded test (scan, BIST, 1500 core)

I’ve got a couple more - how about:

• Design of AC-JTAG for high-speed differential signals
• Low impact mixed-signal test features

All these issues work to draw the DFT engineer, once upon a time concerned mostly with stuck-at fault coverage and cleverly concocting ATE test modes, deep into the floorplanning, placement, routing and physics of the design flow.  You want test compression? Make sure you understand the router’s scan chain re-ordering  requirements and limitations. Are your ATPG patterns going to smoke your chip?  What happens to your scan chains when your design team decides to use voltage islands?

This is not your daddy’s DFT…

The Cell Broadband Engine, that is.  Neat article over at Evaluation Engineering.  Written bt DFT engineers from IBM and Brion Keller from Cadence, the article details the overall test approach for this multicore SoC.   I don’t know how new the article is, since Cadence released this PR in April of last year.  But it was still an interesting read.

With low pin count (128 pins were used for test) as a key goal, they took advantage of the modularity  by broadcasting scan to all the Synergistic Processor Elements (SPE) cores at once.  In BIST mode they can be tested together or independently.

One of the more interesting bits, I thought, was that for performance and power consumption, much of the data path part of the design was left non-scan.  About 40% of the total design turned out to be non-scan, if I read it right.  I would classify that as ‘partial-scan’.  Anyway, despite the data path being mostly non-scan, they did limit the number of consecutive non-scan stages, enabling them to use ATPG to test it anyway, in sequential mode.

All in all they threw the DFT book at this device, including scan, memory BIST, logic BIST, JTAG and test compression, using Cadence’s OPMISR+ (which should come as no surprise, since that technology was developed at IBM before Cadence bought it).

Impressive job!