DFT Digest

It’s been a long time (2 weeks) since my last post; I’ve been enjoying my holiday, thank you very much. I hope you all have too!

It’s actually exactly 1 year since my first post, even though I didn’t get real active until August or so, and didn’t start really telling anyone about the blog until around ITC time. I hope to keep up the momentum in this new year, and spread the word to encourage participation. There’s a lot of good that can come from communicating with one’s colleagues. Right?

Last year, among other things, I did one semi-complete series on test compression, and then started a thread on developing a DFT plan, which I’d like to pursue in the coming weeks. I tried last year to keep on top of industry news items, and I’ll try to keep that up also. I’d like to work up a DFT calendar, similar to the IEEE Test Technology Technical Council (TTTC) calendar that is sent to members. We’ll see.

Look also for extended series on other subjects such as JTAG, ATPG and BIST technologies. I’m very interested in all of them, and the more I write about them, the more I learn!

So many resolutions, so little time..

And I can’t stress enough how important it is to have community participation - please take time to register (it’s FREE) and comment on the posts! Add your two cents to what I hope is an easily accessed base of knowledge for the everyday practice of design for test.

Have a wonderful 2007!

The mission of this website is to educate and discuss electronics design for test. At the end of the day, I want to help anyone trying to tackle the DFT problem, including myself, get through their day. What are we trying to solve? What tools are available to help us solve those problems? How do we know when the design-for-test job is done?

These are the questions I’d like to address in a series of posts (I’ll call it the basics series), which will go on for some time. I will stray into more advanced topics on a regular basis, but, I will advance the basics series just as regularly.

Topics include all those you see on the right side of this web page, in the ‘Categories’ section: scan, ATPG, BIST, JTAG, and any number of other acronyms

Of course, I should repeat often, that I would like feedback, in the form of corrections, criticisms and additional information as often as you readers can find a few spare moments of your busy day.

So please, visit often, and contribute when you can!

“… have been greatly exaggerated” - Mark Twain

In an earlier post, I pointed out an observation seen at DeepChip - that Magma’s DFT strategy was MIA. Well, no sooner did the rumor float than the Twain-like comeback is reported here, by Richard Goering at EE Times. Although, Magma has left the BIST market, it is developing its own ATPG solution, targeting small delay defects, as is the trend in ATPG these days.

The article along with their own press release, also reports that Magma will be present at ITC, with demonstrations of its Blast Create flow’s interoperability with DFT/DFM offerings from several other companies, such as LogicVision, Mentor and Genesys Testware.

I’ll be sure to visit and see what form this interoperability takes…

As I was expecting, as ITC comes upon us, the press releases will start up. Today’s EETimes on-line contains an article entitled “Synopsys Develops New ATPG Technology“. That’ll catch a DFT person’s eye, for sure.

If you read the article, it talks about small delay defects in sub-90nm processes. The new technology will take PrimeTime info and direct the ATPG tool to target paths with the least slack when attempting to catch faults, instead of the easiest ones, which is what current ATPG tools do (probably to make pattern generation faster). Sounds like a good thing to do. I wonder what the ATPG run-time will look like…

This sounds a whole like what Cadence advertises with their Encounter True-time Delay Test, but I haven’t studied that product. Anybody out there have hands-on with it?

Synopsys is not revealing details until ITC, so I guess…

…only time will tell.

A week from today, and ITC will be kicked off in Santa Clara, CA. I’ll be in attendance - specifically, sitting in a tutorial about DF… wait for it … M! Marketing, Manufacturing, Moola, it doesn’t matter, whatever it is, it is driving the forecast for the EDA industry for the next couple of years. See this item in todays on-line version of EE Times. I believe DFM has proven it’s not completely hype; it’s agreed to be absolutely necessary at 65nm and beyond. But I think people also agree it’s the next little tech-bubble, destined for shake-out and consolidation.