DFT Digest

I know, education is always good, but just how much effort should we as DFT Engineers put into educating designers about the whys and wherefores of design-for-test? Do your pleas for test access/features either turn into an endless negotiation, or fall on deaf ears altogether? Of course, test education for engineers and managers is an on-going issue for Test professionals. Committees have been formed over the years: the TTTC TAC, the newly formed TMAG.  So how do you communicate your requirements?

John Eaton writes in a comment posted to the tutorials/resources page:

I am looking for that one document that you can give to a component designer and say “Here, follow all these guidelines and we can test your stuff”.

My reply to him was that in my opinion, it doesn’t exist. And even if it did, there’s a good chance it would never get read. You can lead a horse to water, but you can’t make him drink. So what to do?

My suggestion was to generate checklists to be included in the discussion during design reviews. These DFT checklists provide a documentable set of guidelines and requirements - and very important - a place to justify and or itemize mitigating factors for DFT features that were excluded for any reason.

I have an example of such a checklist that I’ve used in the past (here it is in PDF format - it’s not all-inclusive, I’m sure, but it’s a start).  If nothing else, as long as the DFT Engineer is given the floor for a few minutes during design reviews, the issues contained within the document can be discussed.

So for all you readers out there: what kinds of documents and procedures do you have in place to make sure that Test gets a voice during the design process?

Engineering is not cool. Probably hasn’t been for a generation and a half now. I have a solution - we should hire Paris Hilton, Lindsey Lohan and Britney Spears (and of course! We’ll bring in someone like Brad Pitt for the girls) to do engineering PSA’s (”You know what I like between me and my engineer? Nothing…”). Nope - what do we get? Al Yankovich singing “White and Nerdy”. ROTLOL. Well, we bring it on ourselves. Live long and prosper.

All kidding aside, engineering education, and attracting local talent is on a lot of people’s minds these days. During the keynote at last week’s DesignCon in Santa Clara, Dr. Leah Jamieson outlined some of the efforts going on to make better engineers out of engineering students.

But what about getting kids into engineering school in the first place? Math and science classes at the k-12 level don’t seem to be holding the kid’s interest. I mean, I’ve helped my daughter with her science homework, and I’m bored.

In an article from the EDN website, TI CEO Rich Templeton remarked, “We all need to give back by [...] encouraging k-12 kids to take an interest in math and science. We have to help attract talented people to engineering and make ours a stronger profession”. But really, as all you inguneers out there know, engineering!=math+science anyway It’s a creative experience. And that’s what we should stress from the start.

Some suggest not bothering. In fact I blogged about it soon after I started this blog, way back in March 2006 - at the time there was a reader’s opinion thread running through EE Times about whether you as an engineer would encourage your child to do the same.

Then recently, I saw an article by Howard Johnson, PhD. over at EDN, in which he talked about a letter he received from a high school student asking questions about how he became interested in his profession, what goals students should have with respect to their education, and how science education helps him in his everyday life. Johnson offered some excellent answers to the questions.

His main advice? Get a good hobby. Seriously - it doesn’t matter what the hobby is, but if it engages you, it will drive you to learn and be good at something, which, for lack of a better way of saying it - can create demand for you. He very succinctly points out that “People lacking useful skills or knowledge are forced to trade their time for money. Time is all they have to offer.”

Good advice, no matter the profession…

If 2005 was the first time ITC had been held west of the Mississippi, then this year marks the International Test Conference’s first visit to the left coast. What better place than somewhere with more engineers per square mile than perhaps anywhere on the planet? The bay area! Santa Clara convention center, October 22-27.

So what’s on the agenda this year? The theme is “Getting More Out of Test“, apparently referring to the ever expanding test related activities throughout the design flow, from beginning to end. To this end, there will be diverse activities relating to everything from DFT to yield management. It’s pretty well rounded, although the more popular topics are high-speed test & measurement, debug & diagnosis, and mixed-signal test. DFM and DFY are covered by the keynote, a tutorial and a full workshop.
It seems all the big DFT vendors will be there, Mentor, Synopsys, Cadence (unless they’re feeling squirrely like they did at this year’s DAC), SynTest, LogicVision, Magma, and Novas are all on the list. ATE vendors Advantest, Agilent and Credence are there also. Hmmm… where are Teradyne and LTX?

So many topics, so little time. Are you going? And what are you going to see?

Just a short note this afternoon, after 5 hours of trying to make head or tail of some pattern failures on the tester. The message is: DFT and design engineers, spend some time on the tester! It will open your eyes to the pain experienced by test engineers, caused by your lack of communication or attention to detail, or both. Oh yeah, it’ll also make you realize that certain ATE developers have not yet started developing software reliable enough to be classified as “modern”. But that’s another story.

Anyway, I’m not trying to be a hardass (after all, I’m dissing myself here), but it’s a fact: if you’re passing vectors to a test engineer, who has relatively little knowledge of the chips internals compared to you, if you don’t disposition every device pin as “important” or “mask out”, you will very likely get test vectors shoved back in your face.

The reason is that most of us write simulations with very narrow purpose. So “good” results are normally based upon the behavior of very few pins. The rest of the pins are “don’t care” to you, but happily translated into relevant, strobe-able, events in the test pattern.

If you deal with large ICs, it’s very likely that you don’t even have all the physically accurate models contained in the testbench you’re simulating. What do you care if the real processor’s in there? You’re writing a simple boundary scan test! Your JTAG works, but the processor interfaces are all screwy.

The other thing that was triggered in my mind as I was fighting the ATE today: I must, with every design for test trick available, make sure that the next chip can be tested on a much, much simpler tester.

Have a great weekend!

It was a grueling interview (not!). My prospective manager sat me down in front of his desk, looked at my resume, which contained a summary of my classwork to date (I was up for an intern position), looked up and asked, “Do you like hardware or software better?”

“Both, I guess. I’d say 50-50″, was my reply. Pretty crappy, non-committing answer in retrospect. But I’ll cut myself some slack, it was the first job interview of this 23 year-long so-called career. I didn’t need the technical interviewing skills again for 7-8 more years.

The manager got up and said, “Great! Let me introduce you to Howard over here, he’ll take you to the test floor”. A one question interview!

The test floor was a strange, wonderful place back then. Filled with an assortment of gadgets and gizmos I’d never seen before.  Howard ignored most of it, and led me over to the Fairchild Sentry 20/21 testers, and said “This is what we work on”. It was a big computer, with a mag-tape drive, and a bundle of wires leading to a mounted box, about 2 feet square on its face, and a smaller box with buttons and lights set on top of the mounting frame. A desk with a Hazeltine computer monitor (with built-in keyboard) sat next to the mounted box, called the ‘test head’.

Wow, a hundred years ago… 2-3micron nmos technology, maybe thousands of transistors stuffed into 8 and 16-pin DIP packages. Functional tests, ones and zeros crafted by hand or clever text editing.

I walked onto a test floor a couple of weeks ago, and ran into an old test engineering acquaintance of mine. He was working on a Teradyne Flex system. I looked at the the desk and saw slick graphics and spreadsheets sprawled out across two monitors. An oddly familiar look to it… “It’s Windows XP!”, he said with a grin.

Ahh yes, the ATE world has evolved into an upright position - you can now play Freecell while waiting for your test to run!